【电磁技术在线】【EMC篇】- 6. PCB规则

讲师：Longfei Bai

00：00 内容介绍

01：50 信号完整性规则

02：50 电源完整性规则

04：00 EMC规则

06：15 boardcheck 工作流程

07：40 第一步：标注线路

11：30 第二步：标注元件

13：00 第三步：选择规则

14：00 第四步：查看结果

21：10 违规报告

PCB layout need to follow design rules and pass the check (DRC). However, whether PCB can be fabricated and whether PCB will work after fabrication are the two different questions. The user can designate various nets and components that are critical for EMC, such as I/O nets, power/ground nets, and decoupling capacitors. To ensure the PCB work as we designed, we need to take the signals running on the PCB traces into account, and this requires more advanced design rules as explained in this video.

CST BOARDCHECK relieves the tedium and removes the human error by examining each critical net in turn to check that it does not violate any of the selected EMC or SI design rules. After the rule checking is completed, the EMC rules’ violations can be viewed graphically or by report (new in 2021).

SI Rules

• [3] Differential Net Isolation

• [5] Differential Net Running Skew
  

• [13] Net Length

• [16] Net Stub

• [21] Routing between twoReference Planes

• [22] Single-Ended Net Isolation

• [23] Unconnected Via Pads

• [24] Via Clearance Overlap

• [25] Via Stub

• [26] Via to Net Coupling

PI Rules

• [1] Decoupling Capacitor Density

• [2] Decoupling Capacitor Distance to Via

• [9] IC Power/Ground Pin-Via Distance

• [10] Narrow Power/Ground Traces

• [17] Power/Ground Trace Decoupling

• [18] Power Net Overlapping

• [19] Power Pin Capacitor Distance

• [20] Power Via Density

EMC Rules

• [3] Differential Net Isolation

• [4] Differential Net Matching

• [6] Distance from Filter to Connector

• [7] Distance from Oscillator to Clock Driver

• [8] Exposed Trace Length

• [11] Net Changing Reference

• [12] Net Crossing Split

• [14] Net Near Connector Net

• [15] Net Near Edge of Reference

• [22] Single-Ended Net Isolation