SI-TD (Signal Integrity Time Domain)

Home: SimulationSI TD Analysis

The aim of a SI-TD task is to analyze the transmission behavior on certain signal nets by given voltage excitations and (non-linear) loadings on one or more signal pins of I/O devices.  The transmission behavior includes effects like transmission delay, reflection with over- and undershoots, and cross talk. The result of a SI-TD task is not an equivalent circuit that has to be further processed in a circuit simulation. The result is rather a set of voltage and current curves from the related component pins which is the most important information for signal integrity analysis. The figure below shows the corresponding dialog box:

 

 

Restrict pin list to active circuit signal pins:

The button is activated by default. This is due to the fact that this kind of analysis is performed on signal nets in combination with active I/O devices (see I/O Device Modeling). If the button is unchecked all components will be listed.

 

Only include pins of 'signal' type net classes:

The button allows a further restriction (see explanation above). If activated only pins connected to nets of net class type signal will be displayed. This prevents the user from getting pins which are not connected to fully specified nets.

 

The Available pins frame contains all pins to  which active I/O device models have been assigned  (see I/O Device Modeling). By default, all available components are expanded in order to display the corresponding pins. In order to collapse all pins from all components at once, the user has to right mouse click and pressing Collapse All inside the pull-down menu.

 

Excitations/ports frame

In order to define a signal integrity task, the user has to select a certain pin inside the Available pins frame and shift the pin by using the right-direction arrow to the Excitations/ports frame (or by dragging with the mouse). The program recognizes the corresponding net that the selected pin is connected to. Furthermore the program considers additional nets which are separated by passive 2-pin components (i.e. resistors) from the selected nets using the selection mechanism of the Selection Manager. Finally the program adds all pins of other components which are connected to the recognized nets and where I/O devices are assigned (see I/O Device Modeling) :

 

 

In the figure above just pin IC100-C19 of net net7699 was shifted to the Excitations/ports frame by the user. The other net ADDR(5) was recognized by the program and the corresponding pins of the further components were entered automatically. In order to remove a certain pin (or group of pins), the pin has to be selected and shifted by using the left-direction arrow  (or by dragging it with the mouse).

 

Pin: Displays the pin which was either shifted from the Available pins frame by the user or added automatically by the program. The field can not be edited.

 

Net: Displays the corresponding net of the corresponding pin. The field can not be edited.

 

Model: Displays the I/O device model assigned to the pin. Two kinds of active circuit models are available: a simple Pulse model (default) or a more sophisticated equivalent circuit extracted from an assigned IBIS model. Both types of models can be used to define a Differential pair from the corresponding pin and a further pin (see I/O Device Modeling). The field can be edited by simply double-clicking on it with the left mouse button.

 

Stimulus: references to a pre-defined Stimulus (see Stimulus Editor).

 

Termination: Allows the user to add a termination network between the pin and the connected net on the PCB from a predefined list (see I/O Device Modeling). This functionality is useful if the user wants to perform a quick what-if analysis without having to change any layout in the first place.

 

The Used nets/Used components frame displays all nets which were recognized by the program due to a certain pin selection (see left column). In addition, all passive two-pole components which are connected between the listed nets are displayed in the right column. The green square behind the component tells that a valid model has been already defined and the equivalent circuit for the whole signal path can be automatically completed.

 

 

 

Simulation settings frame: In order to set-up a complete transient task, only one parameter has to be set:

In addition, the user can activate the Eye diagram button which enables an additional output of the simulation results in eye-diagram style. If this button is activated the user has to specify a reference stimulus and the number of bits in order to derive the unique time frame for the eye diagram.

 

Specials settings

Pressing the Specials... button opens a separate dialog box including the following parameters:

 

The Meshing Settings frame includes the following four parameters (see also 2DTL Meshing tab):

 

The Model Settings frame includes the following two parameters (see also 2DTL Modeling tab):

 

The IBIS Settings frame includes the following two parameters (see also Signal Modeling):

 

The Solver Settings frame includes a single parameter:

 

Starting the calculation

Pressing the Start button starts the signal integrity analysis. This means, in a first step, the program will launch the 2DTL meshing and modelling process (see 2DTL). Afterwards, in a second step, a transient task including the complete circuit will be generated in CST DESIGN STUDIO and the circuit simulation will be started. Information on the status of the simulation process will be given in the Message Window. After the circuit simulation has finished the voltages and currents curves will be displayed in CST DESIGN STUDIO according to the listed pins inside the Excitations/ports frame.