3DPEEC

Home: Modeling3D (PEEC)

The Partial Element Equivalent Circuit (PEEC) method divides a selected 3D structure (including conductors and dielectrics) into a mesh of short conductive segments and small conductive and dielectric areas. Constant currents in the segments and constant charges on the areas are assumed. There are different types of PEEC methods that differ in the way they treat retardation effects and in the way they handle dielectrics. The common feature of all types of PEEC methods is the transformation of the electromagnetic field problem into an electric network that can be simulated with a network simulator in time and frequency domain. Because of the electric connection of the conductive segments in the network simulator, the models work for low frequency and DC.

CST PCB STUDIO uses a quasi-static PEEC approach. The magnetic coupling between the conductive segments is done by inductive coupling devices and the electric coupling between the conductive areas is done by capacitors, which takes into account the impact of the dielectric areas. The size of the circuit can be reduced by the amount of the dielectric areas and this is a big advantage of this approach but also the reason for limitations on the maximum allowed frequency. The longest distance between two coupled elements (segments or areas) limits the maximum frequency range of the whole circuit. The maximum valid frequency is evaluated by the program automatically.

There are many applications of the PEEC method and CST PCB STUDIO features additional approximation tools in order to enable the usage for complex PCBs. But the most appropriate applications for this method are boards with a small number of layers, where there is no reference plane with clearly defined characteristic impedances.  This means that in case that the conductors cannot be modeled as microstripes or striplines, due to the absence of a ground from which to determine the characteristic impedance, the 3D PEEC method is most suitable.

The figure below shows the dialog box for the 3DPEEC solver. It consists of three separate tabs for Selection, Meshing and Modeling. In the upper left corner the number of the currently Selected nets is shown. At the right hand side there is the field Length units which allows the user to select a certain unit. Changing the unit does not affect any dimensions. Specific length settings can be made in the Meshing tab only.

 

Number of elements

The frame is folded by default and has to be expanded by clicking on the +-sign first. It  includes information which is generated during the meshing process (see 3DPEEC Meshing tab).

 

Selection tab

The selection tab enables the user to select the nets which should be meshed and modeled. It is identical to the 2DTL Selection tab (see 2DTL Selection tab).

 

3DPEEC Meshing tab

The Meshing tab enables the user to enter all settings which are necessary to divide the selected nets in capacitive areas and inductive segments:

 

 

 

Model net class "ground" / "power" as reference

The idea of the static PEEC method is first to transform the mesh of capacitive areas and inductive segments into a set of four matrices (R, L, C, G) by using a static 3D field calculation. In a second step, these matrices will then be transformed into an equivalent circuit. In general, all inductive segments and capacitive areas are represented by corresponding lumped devices. This is true except for "ground" or "power" nets if those nets were checked to be interpreted as "reference" conductors.

For "reference" conductors the electrical potential for the capacitive areas is assumed to be zero and the voltage drop on the inductive segments is assumed to be zero, too. The impact of this boundary condition is considered in the remaining Signal mesh elements (means capacitive areas or inductive segments) - the Reference mesh elements need not to be represented in the equivalent circuit. The advantage is that he resulting equivalent circuit can be reduced significantly. The disadvantage is the currents in the non-ground mesh elements are not known and this limits the range of use for this kind of model (see Create model for EMI analysis).

 

Channel width for net class "ground" / power:

Allows the setting of a channel width that reduces the size of the overall structure to be calculated. This is a powerful feature when modeling transmission lines along or between reference ground layers, because the whole ground or power layer will not be considered but only parts within this specified channel width around the transmission line. Note: The stamp will only be applied to nets which belong to net class ground or power. In order to have the program reduce a certain conductive structure, the user has to make sure that the corresponding net is assigned to net class ground or power first (see Nets and Net Classes).

 

Element size (inside Meshing settings frame):  

Allows the specification of the mesh cell size for the 3D PEEC mesh cells. This value is applied to both, the capacitive areas and the inductive segments.

 

Refine mesh at terminals & vias (inside Meshing settings frame):

This button is activated by default. It forces a refinement of the mesh around specific points at terminals or vias. This allows a better current distribution and leads to more accurate models.

 

Shrink board outline (inside Dielectric settings frame):

Shrinks the overall board when conductors in a small bounded region are selected only. In this case the program avoids meshing the entire dielectric layer of the board but adapts the board outline to an adequate size around the selected conductors.

 

Board Dielectric (inside Dielectric settings frame):  

There are four possibilities of how to treat the dielectric layers during the modeling phase:

  1. layer stack (original): Each dielectric layer will be considered during the capacitance calculation.  This is the most costly but also most precise treatment of the dielectric layers.

  2. average (between signal layers): An averaging of all dielectric layers between two adjacent metallic layers will be done.

  3. average (total board): An averaging between all dielectric layers of the board will be done. This approximation speeds up the capacitance calculation procedure but the user has to be aware of this simplification.

  4. none (uniform): The presence of any dielectric will be ignored. The user is able to define a background dielectric material. Choosing this function makes the capacitance calculation as fast as possible. It can be useful for a rough and quick estimation of the electromagnetic effects or in cases where the capacitive effects of the board are not dominant.

 

The Regions frame is folded by default. It allows the setting of a finer mesh for user defined regions :

 

 

New: Generates a new region item in the Regions list on the left side of the dialog box. When moving the mouse pointer in the Main View the mouse pointer changes to a cross symbol and the user is able to draw a rectangle, which defines the Location and the Size of the new region. All characteristics of the region are displayed at the right hand side:

Duplicate: Duplicates an existing definition.

 

Delete: Removes the selected region out of the list.

 

Show regions: If the button is activated the selected region will be displayed in the Main View.

 

The Geometry simplification frame is folded by default. It allows the user to control the abstraction of the conductive areas which are included within the selected nets.

 

Set default smooth values: Provides a set of values for the three parameter fields below. There are four different sets of values:

Minimum angle for smoothing: Defines the minimum angle

 

Minimum segment length for smoothing: The values are interpreted with the global units.

 

Maximum line deviation for smoothing: Specifies the maximal value which the smoothed polygon is allowed to deviate from the original polygon. The values are interpreted with the global units. Setting this parameter to zero means to switch off smoothing.

 

Consider neighbors while smoothing: This flag prevents the smoothing function from creating overlaps between shapes next to the smoothed one.

 

Note: Any existing area can be simplified with the identical set of parameters outside this dialog box, too (see Smoothing).  The parameters should only be changed by advanced users.

 

Start Meshing:

Starts the meshing, which means the generation of capacitive areas and inductive segments for all selected nets.

 

Show Mesh:

If this button is pressed the PEEC mesh is displayed in two different styles according to the chosen viewer:

 

Case 1: default viewer activated (see View: Options View Options )

For this case the corresponding 3D PEEC mesh will be displayed in a separate window (see also 2D Result viewer) as shown in the figure below:

 

 

On the lower left and right corner the mesh refinement due to the Refine mesh at terminals & vias functionality can be seen. The rectangle in between has a finer mesh due to a refinement region specified with the help of The Regions frame. The meshed structure is displayed with a 2D top view by default, but the meshed structure can be rotated by left mouse clicking in the Main View and drawing the mouse:

 

 

The Navigation Tree on the left side of the window allows the manipulation of the displayed mesh data:

 

 

Case 2: legacy viewer activated (see View: Options View Options )

For this case the corresponding 3D PEEC mesh will be displayed in the Main View as shown in the figure below. On the right side a list of all meshed sub-regions is presented. Character 'L' stands for layer, character 'N' for net and character 'P' for parts. The expression 'iseg' stands for inductive segments and the expression 'careas' for capacitive areas. The Filter field can be used to select any group of elements and change their display by checking the buttons Off, Light or Shade inside the Mode-frame

 

 

The meshed structure can be rotated by clicking into the Main View and moving the left mouse button. Zooming is also possible by using the mouse wheel.

 

Modeling tab

Within the Modeling tab all necessary parameters to control the generation of an equivalent circuit can be entered and the modeling process itself can be started.

 

 

Ohmic losses:

Ohmic losses ( including the frequency dependent skin-effect) must be always considered for PEEC because of stability reasons in the later circuit simulation.

 

Dielectric losses:

Decides whether the loss angle of the dielectric materials shall be taken into account or not.  If this button is activated the frequency dependent dielectric loss is taken into account on basis of a broadband Debye model (see Dielectric loss modeling) .

 

Create model for EMI analysis:

If this button is checked the equivalent circuit model is generated with some additional information in order to enable the export of a field source during the later circuit simulation. Besides checking this button, some additional settings have to be made inside the Export compact source frame (see Export compact model). Note: This button can only be activated if no net of net class ground is selected (see Special treatment of net class ground). If a net of net class ground is found a corresponding error message will be given by the program.

 

Via modeling:

There are two different possibilities of how to consider vias for 3DPEEC. Both approaches are only accurate for frequencies below about 1 GHz.

 

The Parameter calculation frame include all parameters which control the accuracy of the static 3D field calculation. The settings apply for both inductance and capacitance calculation:

 

Calculation method: There are two calculation methods:

Maximum number of elements for complete calculation: Specifies the number of mesh cells up to which a complete calculation will be performed. Calculating capacitances or inductances by using the complete calculation method means, a full and dense equation system of the size of mesh cells must be established and solved. Since this can be a memory and time consuming task, this upper limit can be specified.  If the number of mesh cells exceeds given value the program switches to the step-by-step method without any regard on the accuracy. If a switch has occurred the user will be informed in the Message Window.

 

Search by: In case of the step-by-step calculation method a circular search region has to be defined. This field allows the user to decide whether this region should be defined directly or with some kind of automatism.

Search radius: The interpretation of this value depends on the specified value inside the field Search by:

Tolerance limit for minor couplings: Forces the program to remove all off-diagonal entries of the generated capacitance and inductance matrix which are below the given percentage of their corresponding diagonal entries. This allows the user to generate more sparse matrices and therefore more sparse equivalent circuits.

 

The Export model frame is folded by default. It allows the user to export the generated equivalent circuit into a SPICE compatible sub-circuit:

 

Export to file: Specifies the directory and the file where the sub-circuit should be written

 

Model name: Specifies the name of the sub-circuit

 

Simulator: Allows the user to select a specific SPICE format:

 

Frequency for R/G calculation: A specific frequency must be specified where the ohmic and dielectric losses should be best fitted. Note: For  2D TL models there is a broadband export which doesn't afford to specify a certain frequency (see Export 2D TL model). Due to complexity reasons this is not possible for 3D PEEC.

 

Export Model: This button starts the export

 

The Export compact model frame is folded by default. It only contains the Settings... button which provides an additional dialog box with special parameters. These parameters are necessary to generate a near field distribution during an  AC circuit simulation. This near field distribution can be exported and re-imported as a field source into CST MWS STUDIO in order to calculate the radiated fields:

 

 

The Bounding box of compact source frame allows the specification of the box where the near fields should be calculated by the program:

 

Complete PCB: The bounding box will include the whole PCB specified by the Board Outline

 

Local region: The bounding box will include the selected and meshed structure only.

 

Gap between PCB and bounding box: Specifies the distance between the structure (Complete PCB or Local region) and the bounding box.

 

 Resolution of field points: define the grid (in x-, y-, z-direction) where the near field has to be calculated.

 

In order to force the actual field export, two other settings have to be done. First the corresponding Create model for EMI analysis flag has to be tagged (see above Create model for EMI analysis). Next, two  further parameters have to be set in the corresponding schematic block of CST DESIGN STUDIO: Select the schematic symbol by right mouse click and choose Properties in the displayed pull-down menu. Next, a new dialog box will appear were the Parameters tab has to be selected as shown in the figure below:

 

 

Both fields Export Currents for EMI and Export Fields for EMI have to be checked. During the next  AC task, a corresponding field source file will be written into the sub folder:  "<project folder> \ Result \ DS \ Tasks \ AC,Combine results1 \ Components \ PCBSSCHEM1".

 

 

The  Reduce model frame is folded by default. If the Low frequency reduction button is activated an additional calculation processed is started directly after the actual PEEC modeling. Hereby, all capacitances which belong to a certain net are collected into a single value. In addition, for a number of N pins/terminals on a certain net, N-1 corresponding inductances and resistances are generated. The frequency where the inductance / resistance calculation is performed can be specified within the Reduction frequency field.

 

 

The result is a SPICE sub-circuit (SPICE 2G.6) which represents the low frequency behavior of the structure with a minimal number of device elements (resistors, inductors, capacitors, current controlled voltage sources). The SPICE sub-circuit can be stored with the help of the Save As button.

 

The figure below shows two different nets. The net at the top side is a trace with two terminals (T3, T4). The net at the bottom side is a rectangular area with three terminals (T1, T2 and T5):

 

 

The corresponding SPICE circuit including the low frequency approximation of the structure is shown in the figure below: