IBIS import block
IBIS
models (I/O Buffer Information Specification) provide Input/Output device
characteristics through measured/simulated data. Since the IBIS format
is applicable to most digital components, IBIS models are often available
from semi-conductor vendors' web sites. More information on IBIS can be
found under http://www.eda.org/ibis/
The IBIS Import block may import a component pin, differential pin pairs, a model and a package ("component") from an IBIS file.
When changing the component pin, the associated model will be changed as well.
Changing the component does not influence the pin or model selection.
The buffer type of the imported model - e.g. "Input", "Output", "I/O", "3-state", etc. - is automatically determined.
Dependent on the selected buffer and its settings the IBIS block icon will have a different number of pins
If a component pin is selected to specify the IBIS model, the output/input pin of the IBIS block will show the name of the component pin.
To be able to use IBIS models within the circuit simulation, CST DESIGN STUDIO™ converts the data given in the IBIS file into a circuit model. This procedure is done whenever an IBIS model is selected.
The file that the block refers to is displayed in the Block Properties - General page. The block offers the usual features of File Blocks like browsing for a new file, editing the referenced project, choice of relative or absolute paths, updating file references and recovery of lost files.
Supported simulation types for IBIS models
An IBIS block can be used with all simulation types of CST DESIGN STUDUIO (see S-Parameter Simulation Task and Transient Simulation Task).
Since IBIS output buffer models are time domain descriptions, the usage of IBIS driver models in other than time domain simulations is somewhat limited.
Simplified layout
There are two options how to connect IBIS blocks. Ether the power supply needs to be manually connected or the values defined in the IBIS model definition are used. In the first case the IBIS block shows two additional pins: 'Supply' and 'GND'.
Input type block
Input IBIS buffers describe the passive behavior of an receiving pin. Usually this behavior is non linear.
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Layout with Vcc and GND
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Simplified Layout
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I/O or 3-State type block
Depending on the signal at the enable pin this
bock type represents ether an output or an input buffer.
The polarity of the enable pin is defined by the IBIS model and may be
active high or active low.
Active low means UEnable = 0V and active high means UEnabl
> Vcc/2.0.
The values for polarity and Vcc can be found in the property dialog box.
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Layout with Vcc and GND
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Simplified Layout
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If enabled, this IBIS block acts as a digital driver that drives the 'Out' pin. Its rising and falling edges are triggered by the input signal at the 'Ctrl' pin. The trigger threshold is Vcc/2.0, as defined by the IBIS model.
Differential IBIS models
IBIS file format also defines differential pin pairs. In this case the layout element shows two instead of one input/output pin.
Supported IBIS key words
[Component]
[Package]
[Pin]
If parasitics are given for the selected pin, they will overwrite the values given under the [Package] keyword.
[Diff Pin]
Since no [Series] keyword is supported, only 'quasi' differential models are supported. A delay between the two buffer models is currently not supported.
[Model Selector]
The [Model Selector] keyword is not supported. If given, the first IBIS model will be used.
[Model]
[Voltage Range], [Pullup Reference], [Pulldown Reference], [POWER Clamp Reference], [GND Clamp Reference]
If any the [... Reference] values are given, they will overwrite the [Voltage Range] setting.
[Pulldown]
[Pullup]
[GND Clamp]
[POWER Clamp]
[Ramp]
[Rising Waveform], [Falling Waveform]
Whenever a wave form is given, the [Ramp] keyword is ignored.
If wave forms of more than two load cases are given the first two are used to create the circuit model.
See also
