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Nexxim Simulator > Via Through Hole with Reference
Netlist FormatA via hole instance has the following netlist format: Axxx n1 n2 [D=val]
[DG=val] n1 and n2 are the names of the node attached to the via through hole. The entry COMPONENT=viahole identifies the element as a via through hole. The entry SUBSTRATE=substrate_name identifies the microstrip substrate model name selected for the design (see Selecting a Microstrip Substrate). See the Microstrip (MS) Substrate for information on this substrate type.
Netlist ExampleA21 Port1 net_31 D=0.001 COMPONENT=viahole SUBSTRATE=FR4 where FR4, the selected layout technology or substrate type, has a definition such as: .SUB FR4 MS( H=7.6200e-004 Er=4.4 TAND=0.02 TANM=0 Notes1. [All substrates] If metallization is not specified in the referenced substrate definition, the via element behaves as an inductance only. 2. [Microstrip] To get accurate results,
set H << l,
where: 3. [Microstrip] Radiation loss is included if the cover height is not defined in the substrate type.
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