淘宝官方店 推荐课程 在线工具 联系方式 关于我们 | |
微波射频仿真设计 Ansoft Designer 中文培训教程 | HFSS视频培训教程套装 |
|
首页 >> Ansoft Designer >> Ansoft Designer在线帮助文档 |
Nexxim Simulator > Via Through Hole
Netlist FormatA via hole instance has the following netlist format: Axxx n1 [D=val]
[DG=val] n1 is the name of the node attached to the via through hole. The other node is ground, and is not specified in the syntax. The entry COMPONENT=viahole identifies the element as a via through hole. The entry SUBSTRATE=substrate_name identifies the microstrip substrate model name selected for the design (see Selecting a Microstrip Substrate). See the Microstrip (MS) Substrate for information on this substrate type.
Netlist ExampleA19 Port1 D=0.001 COMPONENT=viahole SUBSTRATE=FR4 where FR4, the selected layout technology or substrate type, has a definition such as: .SUB FR4 MS( H=7.6200e-004 Er=4.4 TAND=0.02 TANM=0 Notes1. [All substrates] If metallization is not specified in the referenced substrate definition, the via element behaves as an inductance only. 2. [Microstrip] To get accurate results,
set H << l,
where: 3. [Microstrip] Radiation loss is included if the cover height is not defined in the substrate definition.
HFSS视频教程 ADS视频教程 CST视频教程 Ansoft Designer 中文教程 |
Copyright © 2006 - 2013 微波EDA网, All Rights Reserved 业务联系:mweda@163.com |