• 首页
• HFSS教程
• ADS教程
• CST教程
• 射频工程师培训
• 微波仪器操作培训
• 天线设计培训
• 射频专业基础课

Ansoft Designer / Ansys Designer 在线帮助文档：

Schematic Editor >
   Wiring Components >
       Nets, Buses, and Bundles           

Nets, Buses, and Bundles

A net or node is a single wire segment or a connected set of wire segments. A node name can contain any alphanumeric characters except the space ( ), ampersand (&), and asterisk (*). See Wiring Components.

Buses and bundles are ways to name multiple related wires, pins and ports conveniently. This section presents the rules for using bus and bundle wire names, and for the separation of sets of connected wire segments into different wires based on different names.

Bus Format

A bus is a collection of schematic wires that are indexes of a base name, e.g., Data[0-31]. A bus is a schematic concept only. In the circuit and layout, all signals are individual.

A bus name consists of :

• A base name. A base name can contain any alphanumeric characters except the space ( ), ampersand (&), and asterisk (*).

• A square or angle open bracket (‘[‘, ‘<’]

• A number, a range of numbers specified with a hyphen or colon (n1-n2 or n1:n2), or a comma-separated list of numbers or ranges.

• A square or angle close bracket

Following are two examples:

DATA[1:5] \\ A bus with five signals

inputbus[1, 3-5, 11-22] \\ A bus with 15 signals

Bundle Format

A bundle is a collection of schematic wires including individual wires and buses, e.g., A,B,C[7-0]. A bundle is a schematic concept only. In the circuit and layout, all signals are individual.

A bundle name consists of a comma-separated list of single wire names and/or bus names. For example:

DATA[1-5],node5

Creating a Bus or Bundle

To create a bus or a bundle, select Draw > Wire to first create a wire, then change the wire’s name to specify more than one signal, in either bus or bundle format. The width of the wire will change to a wide appearance when the number of signals is more than one.

• When a bus or bundle is copied and pasted, its name is lost and it becomes a single-signal wire.

• Drawing a wire by starting at a bus or bundle vertex will extend/add segments to the bus or bundle.

• Drawing a wire by ending on a bus or bundle will extend or add segments to the bus/bundle, unless the wire started at a named wire, bus or bundle. If it started at a named wire, that named wire will be extended, and it will connect to the bus or bundle if the bus or bundle contains the signal(s) in the named wire.

Deleting Wire Segments from a Bus or Bundle

Deleting one or more wire segments will result in the remaining segments of the wire being assembled into connected sets (based on physical and port connections) with each unique set being an independent wire. Only one of the sets will retain the original name. The others become single-signal wires with automatically assigned names.

Naming a Wire in a Bus or Bundle

Selecting one or more connected segments of an existing wire and assigning a name results in the following:

• The wire is broken into sets as if the newly named segment(s) had been deleted. One set retains the original name. The selected segments become a new wire and are assigned the new name. The new name will spread to connected segments that are automatically named, or that have fewer signals than the new name, and those segments will be added to the new wire. Several different wires may result from this operation, each having a different name.

• Thus, renaming a segment of A[0-3] to A[7-0] will rename the entire wire. Renaming a segment of bus B[31-0] to B[0-63] with a sub-bus connected to it, B[16-31], will rename the connected segments of B[0-31] but will not rename the sub-bus, since it is a separate wire. Renaming the end segment of wire A[0-31] to A[0-15] will make that end segment into a sub-bus that is a different wire than A[0-31].

• If a wire with one or more pageports attached is renamed to a different width, the wire will follow naming rules, and any pageports physically attached will also be renamed.

Naming a Pin or Port on a Bus or Bundle

• The name of a pin or port can be a simple signal name, or can specify multiple signals through bus or bundle format.

• Changing the name of a port will change the name of attached wires.

Connections using Buses and Bundles

• Connections between wires, between pins and ports, and between wires and pins/ports depend on widths and names.

• Wire to wire connections are made if one wire contains the signals of the other. Thus, a wire A[0-7] would have 4 signals electrically connected to physically connected wire A[7-4], namely A[4], A[5], A[6] and A[7]. A bundle A,B,C would have one signal electrically connected to physically connected wire A. A wire A,B,C,D would have two signals connected to physically connected wire C,D,E,F.

• Wire to pin or port connections are determined by the number of signals in the wire and pin/port. If the numbers of signals are the same, electrical connections are made in order. If the widths are different, there is no connection.

• Pin/port to pin/port connections are identical to wire to pin/port connections. If the widths are the same, all signals are connected in order. If the widths are not the same, none are connected.

• Changing the name of a wire that is attached to a pin, a port, or another wire may cause connections to be made or broken, based on the considerations above.

Rippers

A ripper is a two-pin schematic connectivity object, primarily for display and compatibility with third party schematic concepts (e.g., Mentor). A ripper can connect to any bus or bundle on one side, and a sub-bus or bundle on the other side. It functions as an extension of the bus or bundle, generally at a 45 degree angle.

                HFSS视频教程                                      ADS视频教程                               CST视频教程                           Ansoft Designer 中文教程

      Copyright © 2006 - 2013   微波EDA网, All Rights Reserved    业务联系：mweda@163.com