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Voltage Source, Gaussian Random Bit Generator with Jitter

Voltage Source, Gaussian Random Bit Generator with Jitter

Gaussian Random Bit Generator Voltage Source with Jitter Netlist Format

The format for a pseudorandom bit generator voltage source with user-definable jitter and Gaussian rising and falling edges is:

Vxxxx n+ n- RBG=4 [VTH=val] [TD=val] [ROUT=val]
[VLO=val] [VHI=val]
[BITWIDTH=val] JITTER=val [JITTER_REPEAT=val] [MAXJITTER=val]
[SEED=val] [SEED2=val] [T3=val] [T4=val]
[BITLIST=#bitlist] [BITFILE=file_reference] [TAPS=[list_of_taps]]
[TONE=val] [M=val]

n+ and n- are the positive and negative nodes.

**Gaussian RBG Voltage Source with Jitter Parameters**
Parameter	Description	Unit	Default
RBG	Random bit generator keyword. Must be specified as RBG=4 to select the Gaussian RBG voltage source with jitter.	None	None
BITFILE	Reference to external file with the bit values	None	None
BITLIST	Explicit list of bits to generate	None	None
BITWIDTH	Duration of bit at the elvel of Vth [Must be greater than 0.0]	Second	1.0e-9
M	Multiplier for parallel sources	None	1.0
MAXJITTER	Maximum absolute jitter deviation	Second	Calculated
JITTER	Standard deviation (s) for distribution of jitter in bit width. Maximum displacement is ±3s.	Second	0.0
JITTER_REPEAT	1 = Use same jitter data on each repeat of BITLIST Otherwise: Random jitter throughout transient	None	0
ROUT	Source output resistance	Ohm	0.0
SEED	Integer seed for random bit pattern	None	None
SEED2	Integer seed for random jitter in bitwidth	None	None
TAPS	Arrayed list of taps for a linear feedback shift register to be used as the bit source instead of BITLIST. The list_of_taps lists the feedback stages inside brackets and using spaces or commas as separators. The first tap number specifies the number of stages in the device. Subsequent taps must be entered in descending numerical order.	None	None
TD	(Positive) delay time to start of bitstream [Must be greater than or equal to 0.0]	Second	0.0
T3	Half the time for the pulse to rise from 25% to 75% of maximum	Second	BITWIDTH/10
T4	Half the time for the pulse to fall from 75% to 25% of maximum	Second	T3
TONE	Frequency to use for harmonic balance analysis, should be a submultiple of or equal to the driving frequency and should also be included in the HB solution setup	Hertz	0.0
VLO	Logic LOW voltage value	Volt	0.0
VHI	Logic HIGH voltage value	Volt	1.0
VTH	Threshold voltage at which BITWIDTH is measured, also initial voltage	Volt	(VHI +VLO)/2

Bit Generator Voltage Source with Jitter Netlist Examples

V23 23 33 RBG=3 VLO=0 VHI=3 JITTER=1

V43 43 53 RBG=3 VLO=0 VHI=3 JITTER=1 SEED2=1023

In the first example (V23), a random bit sequence is generated with random jitter starting from an internally-generated (pseudorandom) seed.

In the second example (V43), the random jitter starts from the given SEED2, and so will be the same each time the simulation is run.Notes

1. The RBG source is a time-domain element, suitable primarily for transient analysis simulations. The RBG source can be used in harmonic balance analysis only when a BITLIST is given. See Using the GRBG Source with Jitter in Harmonic Balance for details.

2. The BITLIST argument is ignored when a file_reference is supplied via the BITFILE argument.

3. Setting 10-90 and 20-80 Rise Times

Parameter T3 sets the 25-75 rise/fall time, Trise(25-75).

• For a 10-90 rise time, set T3 to Trise(10-90)/3.62

• For a 20-80 rise time, set T3 to Trise(20-80)/2.38

For example, to specify a Trise(10-90) of 36.2ps, set T3 to 36.2/3.62=10ps. Similarly, to set a Trise(20-80) of 47.6ps, set T3 to 47.6/2.38=2-ps.

4. When no BITLIST, BITFILE, or TAPS entry is supplied, the RBG voltage source generates a pseudorandom bit sequence, starting from a random seed value. When no BITLIST or BITFILE is present, the optional SEED can be used to control the bit sequence. The SEED must be an integer value (the maximum absolute value is the maximum size of integers on your system). Using the same SEED guarantees that the same sequence of bits will be generated on each simulation.

5. When a BITLIST, BITFILE, or TAPS is supplied, the RBG source generates the specified sequence of 0 and 1 bits, and repeats the sequence until simulation terminates. When a BITLIST, BITFILE, or TAPS is present, any SEED value will be ignored.

6. In all cases, the sequence of generated bits starts after the time delay given by TD, and continues until the stop time (tstop) of the transient analysis is reached. Each bit changes state with rise and fall times given by TR and TF. and bit duration given by BITWIDTH, measured at the threshold voltage level, VTH.

7. When JITTER_REPEAT is set to 1 and a BITLIST is supplied, Nexxim calculates random jitter data for BITWIDTH on the first iteration of BITLIST, then uses the same set of jitter data on each subsequent repeat of BITLIST. This results in a periodic signal suitable for harmonic balance analysis.

8. The following diagram illustrates the RBG operation for a source defined as:

V23 Port1 0 RBG=4 VLO=1 VHI=3 VTH=2 TD=0.5 TR=0.5 TF=1
+ BITWIDTH=3 BITLIST=#101

9. If TD is negative, an error occurs and the source is ignored.

10. If T3 is omitted, T3 is set to BITWIDTH/10.

11. If T3 is negative or zero, an error occurs and the source is ignored.

12. If BITWIDTH is negative or zero, an error occurs and the source is ignored.

13. The JITTER parameter controls the random variations in bitwidth generated for the bitstream. The the optional SEED2 can be used to control the bit sequence. The SEED2 must be an integer value (the maximum absolute value is the maximum size of integers on your system). Using the same SEED2 guarantees that the same sequence of jitter variations will be generated on each simulation.

14. Using an External File

The parameter BITFILE =file_reference refers to an external file containing the bit data. See File References in the Nexxim Netlist File Format topic for details.

The format of the VRBG data file is:

#bitlist

Where bitlist is a sequence of 1’s and 0’s without any whitespace.

15. Using the Guassian RBG Source with Jitter in Harmonic Balance

The Gaussian RBG VCVS with jitter is primarily a time-domain element, best simulated with a time-domain tool such as transient analysis. The RBG source can be used with harmonic balance analysis only when an explicit BITLIST is provided. With a random sequence, the circuit cannot reach a steady state required for harmonic balance. For harmonic balance analysis, one test tone must be a submultiple or equal to the bit-frequency of the voltage source. To ensure that the desired HB frequency is used with a RBG VCVS source, qualify the source by adding a TONE=frequency entry at the end of the instance statement. That frequency also appears as an argument in the .HB statement.

The default bit-frequency is:

1/[(BITWIDTH + [TR + TF]/2) ´ (number of bits in BITLIST)]

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