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Nexxim Simulator >
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Voltage Source, Linear Feedback Shift Register

Voltage Source, Linear Feedback Shift Register

Linear Feedback Shift Register Voltage Source Netlist Format

The format for a linear feedback shift register voltage source is:

Vxxxx n+ n- RBG=5 [VLOW=val] [VHIGH=val] [TDELAY=val]
[TRISE=val] [TFALL=val] [RATE=val] SEED=val
TAPS=[list_of_taps] [ROUT=val] [TONE=val]

n+ and n- are the positive and negative nodes. The list_of_taps lists the feedback stages inside brackets and using spaces or commas as separators. The first tap number specifies the number of stages in the device. Subsequent taps must be entered in descending numerical order.

Nexxim also accepts the following positional syntax in externally-generated netlists:

Vxxxx n+ n- LFSR [(] vlow vhigh tdlay trise tfall rate seed
[list_of_taps] rout] [)]

In this syntax, entries are interpreted by their position in the syntax, left to right.

Note

The LFSR source is a time-domain element, suitable primarily for transient analysis simulations.

**VLFSR Voltage Source Parameters**
Parameter	Description	Unit	Default
RBG	Random bit generator keyword. Must be specified as RBG=5	None	1
M	Multiplier for multiple devices in parallel.	None	1.0
RATE	Data bit rate [Must be greater than 0.0]	Bits/Second	1.0e9
ROUT	Output resistance	Ohm	0.0
SEED	Integer seed for random pattern. A SEED value greater than 0.0 must be supplied.	None	None
TAPS	Arrayed list of taps to be added to feedback chain.	None	None
TDELAY	(Positive) delay time to start of upramp [Must be greater than 0.0]	Second	0.0
TFALL	Falltime from VHIGH to VLOW [Must be greater than 0.0]	Second	0.5e-9
TONE	Frequency to use for HB or other frequency domain analysis, should be a submultiple of or equal to the driving frequency and should also be included in the any frequency-domain solution setup	Hertz	0.0
TRISE	Risetime from VHIGH to VLOW [Must be greater than 0.0]	Second	0.5e-9
VLOW	Logic low voltage value	Volt	0.0
VHIGH	Logic high voltage value	Volt	1.0

Linear Feedback Shift Register Voltage Source Netlist Examples

VLFSR1 node_43 node_53 RBG=5 VLOW=0 VHIGH=1.5
+ TDELAY=1ns TRISE=0.5ns TFALL=0.5ns RATE=1.5ns
+ TAPS=[16 15 12 9 6 3] SEED=1023 ROUT=50

Notes

1. If TDELAY is negative, an error occurs and the source is ignored.

2. If TRISE or TFALL is negative or zero, an error occurs and the source is ignored.

3. If RATE is negative or zero, an error occurs and the source is ignored.

4. A SEED value greater than 0.0 is required.

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