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Voltage Source, Clock with Jitter

Voltage Source, Clock with Jitter

Voltage Clock Source with Jitter Netlist Format

The format for a voltage clock source with jitter is:

Axxxx n+ n- [DC=val] [V1=val] [V2=val] [TD=val] [TR=val]
[TF=val] [PW=val] [PER=val] [JITTER=val] [SEED=val] [ROUT=val]
[TONE=val] [NOISEVEC=[f1,psd1, ... fn,psdn]]
COMPONENT=vjitter_source

n+ and n- are the positive and negative nodes. The entry COMPONENT=vjitter_source is required.

**Voltage Clock Source with Jitter, Parameters**
Parameter	Description	Unit	Default
DC	DC voltage	Volt	0.0
V1	Clock low voltage value	Volt	0.0
V2	Clock high voltage value	Volt	0.0
TD	(Positive) delay time to start of upramp	Second	0.0
TR	Risetime from V1 to V2	Second	0.0
TF	Falltime from V2 to V1	Second	0.0
PW	Pulse width (V2 hold time)	Second	1e100
PER	Nominal period of clock cycle	Second	1.5e100
JITTER	Standard deviation (s) for distribution of jitter in clock period. Maximum displacement is ±3s.	Second	0.0
SEED	Integer seed for random jitter distribution	None	0
ROUT	Output resistance for jitter calculation	Ohm	1.0
TONE	Frequency to use for harmonic balance analysis, should be a submultiple of or equal to the driving frequency and should also be included in the HB solution setup	Hertz	0.0
NOISEVEC	List of shot noise frequencies (f1...fn) and corresponding noise power spectral densities (psd1...psdn), in pairs. The sequence of frequencies must be monotonically non-decreasing.	Hertz, Volt²/Hertz	None

Voltage Clock Source with Jitter Example

A11 net_1 0 v1=0 v2=1 td=0 tr=1.0e-9 tf=1.0e-9
+ pw=4.0e-9 per=10.0e-9 Rout=1.0 jitter=0.5e-9 seed=12345
+ COMPONENT=vjitter_source

Notes

1. The voltage clock source with jitter is supported only for time domain simulations.

2. Only jitter in the overall clock period is simulated. Pulse width jitter is not calculated separately.

3. The jitter that is simulated is typical of Bounded Uncorrelated jitter (BUJ) rather than true random jitter (RJ). It simulates the jitter due to transitions on neighboring traces, and is uncorrelated with transitions on the clock itself. This device is useful for studies of crosstalk and similar effects.

4. The voltage clock source repeats the clock waveform with random variations in the period. (see diagram below):

5. If PW is negative, PER and PW are both set to their default values.

6. If nominal period PER is less than (TF+TR+PW), PER is set to (TF+TR+PW)

7. The period is the nominal value set by the PER entry, summed with a jitter value that is drawn at random from a normal distribution using the JITTER entry as the standard deviation. The maximum jitter is plus/minus three standard deviations. The pulse width (V2 hold time) is not affected by the jitter. The optional SEED can be used to initialize the random number sequence.

8. The clock source is a voltage source in series with resistor ROUT. Output resistance ROUT is inserted (internally) at the output of the source. If ROUT is zero, the source is an ideal voltage source.

9. For harmonic balance (HB) analysis, the analyzed tones must be submultiples or equal to the frequencies of the actual voltage or current inputs to the circuit. To ensure that the desired HB frequency is used qualify the source by adding a TONE=tone_val entry at the end of the instance statement. The tone_val is then used in a subsequent HB statement.

10. Here is the time-domain simulation of this example source, showing the clock waveform with and without jitter:

Here is a graph of the period times:

Here is a histogram of the period times:

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