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Ansoft Designer / Ansys Designer 在线帮助文档：

Nexxim Simulator >
Support for External Models and Interfaces >
   Verilog Library Support       

Verilog Library Support

A Spectre^® netlist can contain include-file references to Verilog^® model files. Nexxim can access the definitions of any models that are instantiated in the Spectre netlist. In addition, you can create schematic components that instantiate Verilog library models.

The Nexxim implementation includes a built-in Verilog compiler. Compiled mode simulation is supported. Each VerilogA cell is compiled into a C++ file and linked into a DLL. This DLL is loaded during simulation. The precompiled cells are used for each subsequent simulation until a recompilation occurs. A cell is recompiled when a it is modified or when different parameter values are passed to it. You can force a recompile with the option ahdl.compiled_mode.use_precompiled_cells=0.

Nexxim also performs encryption and auto-decryption of model files.

Creating a Verilog Component

Supported Verilog Features

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