淘宝官方店     推荐课程     在线工具     联系方式     关于我们  
　
　

微波射频仿真设计   Ansoft Designer 中文培训教程   |   HFSS视频培训教程套装
　

Agilent ADS 视频培训教程   |   CST微波工作室视频教程   |   AWR Microwave Office
          首页 >> Ansoft Designer >> Ansoft Designer在线帮助文档


Ansoft Designer / Ansys Designer 在线帮助文档：

Nexxim Simulator >
Support for External Models and Interfaces >
   Verilog Library Support >
       Supported Verilog Features           


Supported Verilog Features

The following features of Verilog-A are supported in Nexxim.

1. Operators: all except replication operator ‘{{}}’

2. All built-in mathematical functions

a. Basic functions—pow, sqrt, etc.

b. Trigonometric functions

c. Hyperbolic and inverse hyperbolic functions

3. Natures: ‘voltage’

4. Disciplines: ‘voltage’, ‘electrical’

5. Current/Voltage access functions

6. Analog nodes and branches

7. Parameters

a. ‘real’ and ‘integer’

b. Scalar parameters

c. Vector parameters with constant array initializations

d. Value range specification —‘from’ and ‘exclude’, use of ‘inf’

8. Variables

a. ‘real’ and ‘integer’

b. scalar and vector

9. Genvars

10. Vectors

a. Ports declared as vectors

b. Vector variables

c. Vector nodes

d. Vector branches

e. Bit-selects of vector variable/node/branch/parameter

Index of the bit is a loop or generated index-variable

Index of the bit is a parameter

11. Analog contributions, to assign currents or voltages

a. A branch with a voltage contribution in one evaluation and a current contribution in another.

12. Analog sequential blocks containing analog statements

13. Behavioral statements

a. Procedural assignment

b. Control statements (‘if-else’, ‘case’)

c. Loops (‘for’)

d. ‘generate’ loop statement

14. Instantiations

a. VerilogA instantiations

b. Spectre device instantiations

15. User-defined functions

16. Analog operators

a. Time derivative (‘ddt’)

b. Derivative operator (‘ddx’)

c. ‘transition’ operator

d. ‘last_crossing’ function

e. Laplace filters (laplace_zp, laplace_nd)

f. Limited exponention (‘limexp’)

g. Absolute delay operator (‘absdelay’)

h. Slew filter (‘slew’)

17. Analog events

a. Global events

‘initial_step’, ‘final_step’

‘timer’, ‘cross’

18. Noise analysis

a. white noise

b. flicker noise

19. Analysis-dependent functionality using ‘analysis’ function

a. AC stimulus (‘ac_stim’)

20. Compiler directives

a. 'include directive

b. 'define directive to define constants

21. System functions

a. $temperature

b. $vt

c. $abstime

d. $realtime

e. Table based interpolation and lookup function—$table_model (interpolation data either in data file or in VerilogA file).

22. System tasks

a. Simulation control ($finish, $stop)

b. Analog kernel control ($bound, $step, $discontinuity)

c. Display tasks ($display, $write, $strobe, $monitor, $debug)

d. $table_model

Supported keywords, functions, and system tasks

 


$abstime

asinh

if

$bound_step

atan

inf

$debug

atan2

initial_step

$discontinuity

atanh

inout

$display

begin

input

$finish

branch

integer

$function

case

laplace_nd

$monitor

ceil

laplace_zp

$realtime

cos

last_crossing

$stop

cosh

limexp

$strobe

cross

ln

$table_model

ddt

log

$temperature

ddx

max

$vt

default

min

$write

else

module

‘define

end

or

‘else

endcase

output

‘elseif

endfunction

parameter

‘endif

endmodule

pow

‘ifdef

exclude

real

‘ifndef

exp

sin

‘include

final_step

sinh

‘undef

flicker_noise

slew

abs

floor

sqrt

absdelay

for

tan

ac_stim

from

tanh

acos

function

timer

acosh

genvar

transition

analog

hypot

white_noise

analysis

generate

 

asin

ground

 

 

Keywords supported with workarounds

Parsing for these keywords is skipped.


abstol

discrete

nature

access

domain

idt_nature

continuous

enddiscipline

potential

ddt_nature

endnature

units

discipline

flow

 

 

 

Spectre Compatibility

Nexxim VerilogA is compatible with Spectre.

The directive ahdl_include for specifying the hdl file is supported.

HSPICE Compatibility

Nexxim VerilogA is compatible with HSPICE.

The directive ahdl_include for specifying the hdl file is supported.

The option hdlpath for specifying the location of the hdl files is supported.

The environment variable HSP_HDL_PATH for specifying the location of the hdl files is supported.

Hdl files can be specified with or without the extension.

Parameter names to Verilog instances are case-insensitive..

NOTE: While and repeat loops are NOT supported.



HFSS视频教学培训教程 ADS2011视频培训教程 CST微波工作室教程 Ansoft Designer 教程

                HFSS视频教程                                      ADS视频教程                               CST视频教程                           Ansoft Designer 中文教程


　

      Copyright © 2006 - 2013   微波EDA网, All Rights Reserved    业务联系：mweda@163.com