有通信方向 背景的senior IC验证看过来罗~~ 新加坡的工作机会！

Senior Digital Verification Engineer
The position is base on Singapore.
1.5+ years Experienced ASIC, SOC design verification expert with block to chip level
verification experience. Familiar with verification flow and worked on
testbench, testplan, test execution and coverage closure, tape out and silicon
validation.
2. Hands on experience with one of the modern verification methodologies such as
UVM, VMM, OVM, and familiar with constraint random based verification, including
OOP, functional coverage, assertion checker/coverage and virtual interface.
3. Proficient in HVL(hardware verification language) such as System Verilog,
Verilog, System C or Vera.
4. Knowledge and background in networking protocols such as Ethernet, PCIe,
TCP/IP, Serdes, MAC and PHY are preferred.
5. Experience on networking IC design and verification is preferred, especially
ethernet switch, PHY, traffic manager, network processor, switch fabric and
memory sub system projects.
6. The following skills are not required but under consideration: Perl, TLM,
DPI, XACT, XML, PHP, mySQL.
7. Emulation, FPGA verification and IXIA, SmartBit debugging experience are a
plus.
联系方式
QQ：2251638853
Email:2251638853@qq.com

IC验证 方向的 兄弟们 看过来啦~~~~

自己顶下~~