CMOS Technology Characterization for RF design
12-09
Abstract— The design of analog and radio-frequency (RF)
circuits in CMOS technology becomes increasingly more difficult
as device modeling faces new challenges in deep submicrometer
processes and emerging circuit applications. The sophisticated set
of characteristics used to represent today’s “digital” technologies
often proves inadequate for analog and RF design, mandating
many additional measurements and iterations to arrive at an
acceptable solution. This paper describes a set of characterization
vehicles that can be employed to quantify the analog behavior
of active and passive devices in CMOS processes, in particular,
properties that are not modeled accurately by SPICE parameters.
Test structures and circuits are introduced for measuring speed,
noise, linearity, loss, matching, and dc characteristics.
Index Terms—Analog circuits, device noise, mismatch, MOS
devices, RF circuits, technology characterization.
I. INTRODUCTION
AS CMOS technology continues to benefit from both
scaling and the enormous momentum of the digital
market, many high-speed and radio-frequency (RF) integrated
circuits that were once considered the exclusive domain of
III–V or silicon bipolar technologies are likely to appear as
CMOS implementations. However, issues such as technology
development costs, computer-aided design (CAD) infrastructure,
and fabrication turnaround time make it desirable to use
a single mainstream digital CMOS process for all IC products.
“Analog processes” may be approaching extinction.
The design of analog and RF circuits in a digital CMOS
technology faces many difficulties: the set of available active
and passive devices is quite limited, the technology is optimized
for digital design, and the devices are characterized and
modeled according to simple benchmarks such as current drive
and gate delay. While the first two issues can be somewhat
alleviated by circuit and architecture innovations, the quandary
of poor characterization leads to substantial conservatism in
analog design, thus resulting in circuits that do not exploit
the “raw” speed of the technology. In some cases, even
conservatism does not solve the problem, mandating lengthy
iterations in the design. For example, in a narrow-band RF
oscillator, it is difficult to guarantee a correct output frequency
without accurate data on device parasitics and their variation
with process and temperature.
This paper describes a set of technology characterization
methods that provide the basic information required in ana-
Manuscript received August 11, 1998; revised October 26, 1998.
The author is with the Electrical Engineering Department, University of
California, Los Angeles, CA 90095 USA.
Publisher Item Identifier S 0018-9200(99)01651-0.
Fig. 1. Analog design octagon.
log and RF design. It also reviews some relevant modeling
difficulties. Section II presents the motivation for and the
issues related to the task. Sections III and IV deal with
characterization for analog and RF design, respectively. For
the sake of brevity, we use the term “analog” to mean “analog
and RF.”
II. MOTIVATION AND ISSUES
The principal difficulty in using a digital CMOS technology
for analog design is that the process is optimized and
characterized for primarily one tradeoff: that between speed
and power dissipation. By contrast, analog circuits entail a
multidimensional design space. This is illustrated in Fig. 1,
where almost every two parameters trade with each other. The
true severity of these tradeoffs is known only if relevant data
have been obtained for the technology.
The need for specialized “analog characterization” arises
from two types of shortcomings: inaccurate modeling (e.g., the
output resistance of transistors or its nonlinearity) or simply
lack of modeling (e.g., self-resonance frequency of inductors
or matching properties of transistors). While efforts toward
improving submicrometer device models continue vigorously,
scaling appears to degrade the modeling accuracy faster. That
is, it seems that for no generation of CMOS devices have
models been sufficiently accurate.1
It is also important to note the rapid migration of digital
circuits from one generation of the technology to the next.
Analog circuits have historically lagged behind by more than
one generation, failing to utilize the full potential of new
processes or to comply with their supply-voltage scaling. A
solid understanding of the properties and limitations of devices
1 This is the author’s opinion rather than a documented fact.
0018–9200/99$10.00 ã 1999 IEEE
RAZAVI: CMOS TECHNOLOGY CHARACTERIZATION 269
also minimizes the number of design iterations and hence the
time to market.
The above observations indicate that analog design in a new
technology can be greatly simplified if measured data points
describing the analog behavior of devices and subcircuits are
obtained. In fact, such data points do become available as
analog designers begin to use a process, but in an ad hoc
manner and very slowly. A unified effort to collect all of the
necessary data soon after the qualification of a technology is
rarely seen.
Technology characterization for analog design nonetheless
involves a number of difficult issues.
• Owing to the lack of universally applicable analog benchmarks,
many test structures must be built to satisfy the
needs of various systems. Op-amps, filters, comparators,
data converters, oscillators, phase-locked loops, frequency
synthesizers, and RF transceivers incorporate many different
functions that heavily depend on poorly modeled
properties of devices.
• Some device characteristics, for example, capacitor mismatch
and thermal and noise, are difficult to measure.
Thus, proper circuits must be included on the die to allow
reliable measurement.
• Some measured properties are difficult to incorporate in
simulations. For example, the voltage dependence of the
output impedance of transistors cannot be easily included
in the simulation of an op-amp. Such cases may mandate
designing a complete circuit to measure the overall effect.
• The large number of test structures requires substantial
characterization time and effort. It is therefore desirable
to automate the measurements to the extent possible.
• The test structures and circuits must be designed such that
they can be ported into the next generation of the process
with minimal modifications.
It is also beneficial to design two sets of structures: a
comprehensive version to be used in the early phases of a
new technology and a brief version to be included in product
mask sets. The latter proves useful in detecting anomalies in
the process.
III. CHARACTERIZATION FOR ANALOG DESIGN
The device and circuit properties of interest in analog design
can be grouped into six categories:
1) dc behavior;
2) ac behavior;
3) linearity;
4) matching;
5) temperature dependence;
6) noise.
We consider the first five here and noise in Section IV. Our
emphasis is on those aspects that are not modeled accurately
in SPICE simulations.
Fig. 2. AC coupling using devices biased in subthreshold region.
A. DC Behavior
Typical – characterization seeks to minimize the
overall error in the curve fitting procedure, thus incurring
significant relative local errors. While advanced models such
as BSIM3v3 incorporate many parameters to lower such errors,
some submicrometer device properties still defy accurate representation.
For this reason, it is important to have measured
I–V data points in a range suitable to analog design, e.g.,
mV and A/ m.
Subthreshold characteristics of MOSFET’s are difficult to
model. (One version of the BSIM model does represent this
behavior, but it also yields a negative gate-source capacitance
under certain conditions.) In sampled-data circuits, the subthreshold
conduction of switches in the off state, especially
at high temperatures, may lead to significant leakage, thereby
corrupting the stored information. This effect also becomes
important in determining the lower bound on the speed of
dynamic latches in mixed-signal and digital circuits.
A difficulty in subthreshold modeling is dc and ac slope
discontinuity in the vicinity of strong inversion as increases.
In fact, time-domain simulation of circuits in which
MOSFET’s reciprocate between the two regions exhibit substantial
dynamic errors. For example, in two-tone simulations
of RF CMOS circuits, the output spectrum often suffers from
a high noise floor that is an artifact of slope discontinuities in
the device equations. This issue remains unresolved in most
mainstream models.
Subthreshold operation actually proves useful in some cases.
For example, as depicted in Fig. 2, a diode-connected MOSFET
biased in subthreshold exhibits a large incremental resistance,
thus creating a low cutoff frequency in the high-pass
filter formed with By contrast, a resistor of comparable
value would consume a large area and introduce considerable
parasitic capacitance at the output node. The circuit of Fig. 2
can be employed if the subthreshold properties of transistors
are known at different temperatures.
Another troublesome effect is the output resistance of shortchannel
MOS transistors, and in particular its variation with
the drain-source voltage even in the saturation region. Shown
in Fig. 3, this phenomenon causes the intrinsic gain to
depend on the output potential, thereby creating nonlinearity
in amplifiers. Present models include this behavior but with
more than 50% error in some cases. For op-amp design, it is
270 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999
Fig. 3. Measured variation of MOS output resistance versus VDS:
Fig. 4. Capacitance–voltage characteristic of an MOS device along with its
derivative.
also useful to obtain measured plots of as a function of
the drain current for various device dimensions.
B. AC Behavior
The discrepancy between the simulated and measured speed
of MOS devices and circuits continues to haunt designers. For
example, the device models extracted from a wafer often fail to
accurately predict the gate delay of ring oscillators fabricated
on the same wafer.
To obtain a versatile set of data points, ac characterization
of a technology must be performed at both device level and
circuit level. For devices, and must be measured under
bias conditions common in analog circuits, e.g.,
mV and A/ m. For a given
current, [1], indicating that the ’s
encountered in analog applications are much lower than those
measured with the value typically reported for
CMOS technologies.
Another ac device parameter of interest is the nonlinearity of
MOS gate-channel capacitance in accumulation and inversion.
This effect can be better seen by plotting the derivative of
the – data versus the gate-channel voltage (Fig. 4). While
MOS capacitors are quite nonlinear, they nonetheless prove
useful in some analog circuits [2].
MOS capacitors are also utilized as supply and bias bypass
elements (Fig. 5). In such cases, the series resistance of
the capacitor affects the effectiveness of the bypassing. For
example, the resistance can be used to produce a critically
damped response if lead inductance or current slew rates are
Fig. 5. MOS capacitors as bypass elements along with illustration of channel
resistance.
Fig. 6. N-well capacitance in a PMOS differential pair.
Fig. 7. Bias circuit using n-well resistor.
significant [3]. The series resistance is readily calculated in
the strong inversion region [4], but its value in accumulation
must be measured.
Another rarely available process parameter is the capacitance
of the n-well to the substrate. If the source and n-well of
a PMOS device are connected to avoid body effect (Fig. 6), the
n-well capacitance must be taken into account. The capacitance
of resistors made of n-well may also be important. In Fig. 7,
for example, resistor and capacitor isolate the bias
current mirror from the signal path, thus allowing ac coupling
of the input signal. In this circuit, the value of is not critical
so long as it remains much greater than the output impedance
of the preceding stage, but the parasitic capacitance of
attenuates the signal.
For ac characterization at circuit level, frequently used
building blocks such as ring oscillators can serve as test
vehicles. The choice of a circuit for this purpose is determined
by three factors: 1) the complexity and design time of the
circuit, 2) the useful information obtained from testing the
circuit, and 3) the level of difficulty in testing the circuit.
Differential ring oscillators with realistic device dimensions
and bias currents are more widely accepted than single-ended
RAZAVI: CMOS TECHNOLOGY CHARACTERIZATION 271
Fig. 8. Simple comparator for measuring metastability.
topologies. The speed of these circuits and its correlation with
process corner models constitute a more reliable basis for
design than those of ring oscillators using simple inverters.
Another circuit that exercises the intrinsic speed of the
technology is a voltage comparator. Fig. 8 shows an example
where and amplify the input difference and and
perform regeneration after turns off. The regeneration
speed at nodes and can be measured by operating
the comparator near metastability [5], [6] and measuring the
change in the response time for small increments in the input
voltage. In practice, all of the device widths and bias currents
may be scaled up by a factor of 100 so that the currents
provided by and generate moderate voltage swings
in a 50- instrumentation environment. Note that such scaling
does not change the regeneration time constant.
C. Linearity
The linearity of both passive and active devices plays a
critical role in many analog circuits. The value of a resistor
or a capacitor can be expressed in terms of the voltage across
the device as The coefficients
and must be measured for different types of resistors and
capacitors available in a process. Note that the linearity of
polysilicon resistors typically improves with their length [7].
The linearity of op-amps is also of great interest. In a
conservative design, the open-loop gain of the circuit is
chosen large enough to obtain a small closed-loop gain error,
thus guaranteeing that the nonlinearity is of the same order.
However, the low of submicrometer devices makes it
difficult to achieve a high open-loop gain. Furthermore, gain
error per se is not critical in many applications, or it can be
corrected by calibration techniques. Thus, aggressive designs
seek to minimize the nonlinearity by adequate open-loop gain.
This is possible only if the nonlinearity of the open-loop circuit
is well understood.
In a fully differential op-amp, e.g., Fig. 9(a), the nonlinearity
arises from two principal sources: compressive voltage-tocurrent
conversion of the input differential pair and the voltage
dependence of the output impedance of the cascode devices.
As depicted in Fig. 9(b), the first mechanism is measured by
applying a differential input voltage and monitoring the output
short-circuit current. Since the output voltage is constant, the
nonlinearity due to the cascode devices is negligible. For
the second mechanism, as shown in Fig. 9(c), the differential
input is set to zero and the output large-signal impedance is
measured.
To quantify the overall nonlinearity, we utilize the configuration
depicted in Fig. 10, where all the passive devices may
be external for simplicity. Resistors and establish the
bias but are large enough to be considered ac open. With a pure
sinusoid applied to the input and different choices of
the output harmonic contents can be measured and the “static”
nonlinearity of the open-loop op-amp derived.
D. Matching
While matching properties of passive and active devices
have been extensively studied in terms of dimensions and
process constants [8]–[11], actual measurement of mismatches
is often necessary. This is because in addition to fundamental
parameters such as device area, other characteristics such
as “cleanness” of the process determine the magnitude of
mismatches as well.
Measurement of transistor and resistor matching is straightforward.
The test structures must employ many different
dimensions so as to quantify the dependence on the area.
Fig. 11(a) shows an arrangement with a minimum number of
pads for measuring the gate-source voltage of each transistor
in every differential pair. A tail current is drawn from the
common source node of the pair, node or node is tied to
, and the other is connected to ground, thus establishing
the value of Using this technique, the mismatch
can be measured as a function of the drain current. The
resistor–capacitor network prevents oscillations due to large
parasitic inductances in the setup.
It is also desirable to include nominally identical current
sources [Fig. 11(b)]. Since the mismatch between two current
sources depends on both the threshold voltage mismatch
and mismatch [11], [6], measurements on both
structures in Fig. 11(a) and (b) allow for cross checking the
validity of the extracted data.
Measurement of resistor mismatch usually requires a fourpoint
(“force” and “sense”) arrangement so as to avoid resis-
272 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999
Fig. 9. (a) Sources of nonlinearity in a folded-cascode op-amp, (b) measurement of input nonlinearity, and (c) measurement of output nonlinearity.
(Common-mode feedback not shown.)
Fig. 10. Arrangement for measuring op-amp distortion.
tance mismatches due to external connections. The topology
shown in Fig. 12 allows such a measurement with a relatively
small number of pads.
Characterization of capacitor matching is quite difficult.
For small capacitors used in most analog circuits, in the
range of 0.1–1 pF, direct measurement would suffer from
many uncertainties resulting from parasitics in the physical
setup. Thus, the capacitors must be isolated from external
connections by means of on-chip circuitry. Fig. 13 illustrates
an efficient approach to measuring capacitor mismatch [12].
The top plates of and are connected to node , and
a PMOS source follower serves as a buffer. The n-well of
is tied to its source to eliminate the nonlinearity due
Fig. 11. Structures for measuring transistor mismatch.
to body effect. The test proceeds by applying a ramp to
while is grounded, generating a ramp at whose slope
is approximately equal to Next, and
are interchanged, and the output slope
is obtained. The relative mismatch can then be calculated as
(1)
Utilizing only the change in this approach cancels
the effect of three nonidealities: 1) the initial charge at node
, 2) the parasitic capacitance at node , including the input
RAZAVI: CMOS TECHNOLOGY CHARACTERIZATION 273
Fig. 12. Topology for measuring resistor mismatch.
Fig. 13. Capacitor mismatch measurement.
capacitance of the source follower, and 3) the drain-source
impedance of [12]. The measurement must nonetheless
be performed with relatively large voltage excursions so as to
calculate the difference between and accurately.
E. Temperature Dependence
The temperature variations of many device parameters are
not modeled accurately in SPICE. Examples include output
resistance, subthreshold conduction, and capacitances. Furthermore,
the temperature coefficient of resistors and capacitors
must be measured for each technology generation, as it may
depend on doping levels or the type of dielectrics.
In addition to basic device parameters, some other circuitrelated
quantities should also be characterized as a function
of temperature. For example, direct measurement of the variations
of the transconductance, on-resistance, and threshold
voltage provides a more reliable and versatile characterization,
thus simplifying the design procedure. The ac properties of the
technology also vary with temperature. The ring oscillator and
comparator circuits described in Section III-B can serve as
structures allowing the measurement of speed as a function of
temperature.
Owing to the lack of comprehensive data on temperature
dependence of device parameters, a number of important
design questions remain unanswered: How should the bias
currents of an op-amp vary with temperature? What is the
optimum temperature variation of bias currents in a low-noise
amplifier or mixer? How should the tail currents of a ring
oscillator or LC oscillator vary with temperature? To answer
these questions, various dc and ac temperature dependencies
of devices must be measured and incorporated in simulations.
Another useful test structure is a simple bandgap reference
[13]. Depicted in Fig. 14, such a circuit finds wide usage
in most analog and mixed-signal systems. With a simple
Fig. 14. Simple bandgap reference. (Transistor M5 serves as startup.)
version of the reference available in the early phases of
technology qualification, subsequent iterations in the design
are minimized. In addition, measurement of the base resistance
and current gain of individual vertical pnp transistors proves
useful in predicting the behavior of the bandgap circuit.
IV. CHARACTERIZATION FOR RF DESIGN
Most of the analog characterization methods described
above are also essential to RF design. For example, dc and
ac properties, noise, and temperature dependence are critical
here as well. In addition, many RF characteristics must be
measured at device and circuit levels to facilitate the design
of highly integrated RF systems.
A. Device Properties
The severe tradeoffs among noise, frequency of operation,
gain, and power dissipation in RF circuits limit the number
of active devices in the signal path of some building blocks.
Examples include low-noise amplifiers (LNA’s), mixers, and
oscillators. Consequently, passive monolithic devices that exhibit
little loss and operate as high-quality loads or interfaces
can greatly simplify the design. Inductors, capacitors, varactors,
and transformers appear in many RF IC’s today.
While the value of spiral inductors can be calculated with
reasonable accuracy [14], the and self-resonance frequency
are much more difficult to predict. The distributed nature of
the spiral and the underlying substrate usually requires the use
of finite element analysis, especially for complex structures
such as stacked inductors [15]. Furthermore, the dependence of
inductor parameters upon line width and spacing, the number
of turns, the size of the opening in the middle, and the type of
“shield” placed underneath the inductor [16] make it difficult
to choose the optimum structure for a given frequency of
operation. For these reasons, it is beneficial to obtain measured
data for parameters of inductors with different geometries.
Shown in Fig. 15 are two structures of interest in RF design
[21].
A simple method of measuring the and the self-resonance
frequency of inductors is illustrated in Fig. 16. Identical
inductors and together with the negative- pair
and form an oscillator. If the capacitance contributed
274 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999
(a) (b)
Fig. 15. (a) Inductor with broken shield and (b) stacked inductors.
Fig. 16. Arrangement for measuring self-resonance frequency and Q of
inductors.
Fig. 17. Floating varactor in CMOS technology.
by the transistors and the output buffer is negligible with
respect to the parasitic capacitance of and the circuit
oscillates at In this case, the buffer can incorporate small
devices so as to present minimal capacitance to the oscillator
(at the cost of signal attenuation) because most spectrum
analyzers can detect the existence and frequency of even weak
oscillations.We also observe that if the tail current is decreased
to the point where the oscillation is near failure, the negative
transconductance provided by and is approximately
equal to the equivalent parallel resistance of the inductors,
i.e., Thus, The
value of under this condition can be measured for and
which are identical to and The key point here
is that the and self-resonance frequency are measured in a
realistic environment.
Varactors built in CMOS technology also suffer from a
low quality factor. Depicted in Fig. 17, a floating varactor
exhibits substantial series resistance due to the n-well material.
Direct measurement of the varactor provides an equivalent
lumped value for the three-dimensional distributed resistance
of the structure. MOS varactors have also been studied recently
[22]–[24] and merit characterization in each process.
Another useful passive component is a transformer.
Monolithic transformers suffer from parasitic capacitances
and frequency-dependent voltage and power loss [25], [26].
Measurement of these parameters can lead to a model suited to
circuit simulations. For interfaces where voltage gain is more
important than power gain, the 2 : 1 transformer of Fig. 18(a)
may prove useful. A simple transformer-based oscillator, e.g.,
that in Fig. 18(b), can also yield the self-resonance frequency
and loss of the structure.
B. Noise
The thermal noise of submicrometer MOS transistors
does not satisfy the long-channel approximation
[17]. Depending on the bias conditions, the
“excess noise factor” may be quite higher than 2/3, an effect
not included in most SPICE models. More accurate models for
the channel noise are described in [18]. But two other thermal
noise mechanisms merit characterization as well. Illustrated
in Fig. 19, the first results from the capacitive coupling of
the drain noise current to the gate, introducing a physical
gate noise current [19], [20]. To measure this phenomenon,
different noiseless impedance levels can be placed in series
with the gate while other parameters remain constant, thereby
producing different noise levels in the drain current.
The second effect arises from the modulation of the threshold
voltage by the body thermal noise [Fig. 19(b)]. Note that,
owing to the distributed nature of the body resistance, this
issue exists in differential circuits as well. Fig. 20 plots the
simulated noise figure of a cascode stage as the body resistance
varies, revealing a degradation of approximately 0.2 dB. The
principal difficulty here is accurate prediction of the local body
resistance—the three-dimensional structure may require the
use of device simulators.
The noise of MOSFET’s has also created challenges in
analog and RF design. For noise calculations, the technology
constant in must be measured for
both PMOS and NMOS devices. In reality, the dependence on
and even may be of the form where and
are nonunity exponents. These parameters too may vary from
one process to another.
Direct measurement of device noise is quite difficult simply
because the values to be measured are too small to be sensed
properly by typical instrumentation. Some amplification is
therefore necessary, but the noise contributed by the gain
RAZAVI: CMOS TECHNOLOGY CHARACTERIZATION 275
(a) (b)
Fig. 18. (a) A 2 : 1 transformer and (b) a transformer-based oscillator.
(a) (b)
Fig. 19. Illustration of (a) drain noise capacitively coupled to gate and (b)
modulation of threshold voltage by body thermal noise.
Fig. 20. Noise figure of a cascode amplifier as a function of the body
resistance (modeled by a lumped resistor in series with the substrate terminal
of each device).
stage(s) must be sufficiently lower than that of the device
under test.
Fig. 21 shows an arrangement for measurement of both
thermal and noise of MOSFET’s. Biased by means of
and the transistor under test, forms a cascode
configuration with providing an intrinsic voltage gain
of approximately The external resistor is
chosen to be higher than the output impedance of the cascode
to avoid lowering the voltage gain. A high value for also
minimizes its noise contribution. Note that the effect of the
noise generated by is negligible at low frequencies if
exceeds approximately four.
The large value of together with typical bias currents
used in the test translates to a relatively high supply voltage,
but can be maintained below the maximum allowable value
to avoid stressing the cascode device. To minimize drifts in
some dc feedback may be added from to the gate of
The source follower lowers the output impedance
of the circuit, an important provision because the input noise
current of the external sensing circuitry may be significant.
Fig. 21. Arrangement for measuring device noise.
Since power supplies and bias networks typically exhibit
considerable noise, the circuit of Fig. 21 must be operated
from a low-noise battery. Furthermore, the supply line, the
gate-source bias of , and the gate bias of must be
bypassed to ground by several capacitors ranging from a few
nanofarads to several hundred microfarads so that unwanted
low-frequency and high-frequency noise components are suppressed.
C. Circuit Properties
The design of such RF building blocks as LNA’s, mixers,
oscillators, modulators, and power amplifiers (PA’s) heavily
depends on the overall transceiver architecture and the intended
wireless standard. For this reason, it is difficult to
introduce test vehicles that provide useful data for various RF
applications. For example, the design of an LNA that must
drive a 50- load may be significantly different from one
that need not. Thus, RF characterization circuits are somewhat
specialized.
A critical issue in today’s RF CMOS design is the substantial
variability of device and circuit parameters with process
and temperature. While analog circuits have for decades utilized
tracking and cancellation techniques to achieve welldefined,
stable parameters, RF circuits still lack such precautions.
For example, since the gain of LC-tuned amplifiers
is a strong function of parasitic capacitances, it must be
measured on various wafers from different lots so as to obtain a
realistic distribution. Similarly, the center frequency of typical
oscillators, e.g., that in Fig. 16, must be measured on many
dice and at temperature extremes to yield the required tuning
range.
276 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999
Fig. 22. Arrangement for measuring phase and gain mismatch between two
RF mixers.
Matching properties play an important role in many RF
circuits. Fig. 22 illustrates an example of measuring the
phase and gain mismatch between two RF mixers. The highfrequency
inputs and directly drive the two mixers to
avoid mismatches in the external connections. If the frequency
difference between the two inputs is relatively small,
and have a low frequency, and hence their phase and
amplitude mismatch can be measured with high precision.
Another useful benchmark is a frequency divider. Divideby-
two circuits and dual-modulus dividers find wide usage in
quadrature generation and frequency synthesis, respectively.
At present, the power–speed tradeoff of these circuits is
much more severe in CMOS technology than in bipolar
implementations. Furthermore, significant discrepancy is often
observed between the simulated and measured speed–power
tradeoff of the circuits. Thus, measured data corresponding to
different divider topologies prove valuable.
PA’s are also critical components whose design remains
a formidable task. Owing to the large current and voltage
changes that the output transistor in a PA experiences, accurate
device modeling to predict efficiency and linearity has become
a serious issue. As a result, PA design heavily relies on the
data measured for single transistors. Large MOSFET’s with
proper layout and pad configurations must be included to allow
high-power, high-frequency characterization.
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[13] T. L. Brooks and A. L. Westwick, “A low-power differential CMOS
bandgap reference,” in ISSCC Dig. Tech. Papers, Feb. 1994, pp.
248–249.
[14] H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,”
IEEE Trans. Parts, Mater., Packag., vol. PMP-10, pp. 101–109,
June 1974.
[15] R. B. Merril et al., “Optimization of high Q inductors for multi-level
metal CMOS,” in Proc. IEDM, Dec. 1995, pp. 38.7.1–38.7.4.
[16] C. P. Yue and S. S. Wong, “On-chip spiral inductors with patterned
ground shields for Si-based RF IC’s,” in Dig. Symp. VLSI Circuits, June
1997.
[17] A. A. Abidi, “High-frequency noise measurements on FET’s with small
dimensions,” IEEE Trans. Electron Devices, vol. ED-33, pp. 1801–1805,
Nov. 1986.
[18] Y. Tsividis, Operation and Modeling of the MOS Transistor. New
York: McGraw-Hill, 1987.
[19] A. van der Ziel, “Gate noise in field effect transistors at moderately high
frequencies,” Proc. IEEE, vol. 61, Mar. 1963, pp. 461–467.
[20] D. K. Shaeffer and T. H. Lee, “A 1.5-V 1.5-GHz CMOS low noise
amplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745–759, May 1997.
[21] B. Razavi, “Challenges in the design of frequency synthesizers for
wireless applications,” in Proc. CICC, May 1997, pp. 395–402.
[22] C.-M. Hung et al., “High-Q capacitors implemented in a CMOS process
for low-power wireless applications,” IEEE Trans. Microwave Theory
Tech., vol. 46, pp. 505–511, May 1998.
[23] T. Soorapanth et al., “Analysis and optimization of accumulation-mode
varactor for RF IC’s,” in Symp. VLSI Circuits Dig. Tech. Papers, June
1998, pp. 32–33.
[24] R. Castello et al., “A 30% tuning range varactor compatible with
future scaled technologies,” in Symp. VLSI Circuits Dig. Tech. Papers,
June 1998, pp. 34–35.
[25] J. R. Long and M. A. Copeland, “A 1.9 GHz low-voltage silicon bipolar
receiver front-end for wireless personal communication systems,” IEEE
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[26] A. M. Niknejad and R. G. Meyer, “Analysis and optimization of
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May 1997, pp. 375–378.
Behzad Razavi (S’87–M’90) received the B.Sc. degree
from Sharif University of Technology, Tehran,
Iran, in 1985 and the M.Sc. and Ph.D. degrees
from Stanford University, Stanford, CA, in 1988
and 1992, respectively, all in electrical engineering.
He was with AT&T Bell Laboratories, Holmdel,
NJ, and subsequently Hewlett-Packard Laboratories,
Palo Alto, CA. Since September 1996, he has been
an Associate Professor of electrical engineering
at the University of California, Los Angeles. His
current research includes wireless transceivers, frequency synthesizers, phaselocking
and clock recovery for high-speed data communications, and data
converters. He was an Adjunct Professor at Princeton University, Princeton,
NJ, from 1992 to 1994 and at Stanford University in 1995. He is the author of
Principles of Data Conversion System Design (New York: IEEE Press, 1995)
and RF Microelectronics (Englewood Cliffs, NJ: Prentice-Hall, 1998), and the
Editor of Monolithic Phase-Locked Loops and Clock Recovery Circuits (New
York: IEEE Press, 1996).
Prof. Razavi received the Beatrice Winner Award for Editorial Excellence
at the 1994 ISSCC, the Best Paper Award at the 1994 European Solid-State
Circuits Conference, the Best Panel Award at the 1995 and 1997 ISSCC,
and the TRW Innovative Teaching Award in 1997. He is a member of the
Technical Program Committees of the Symposium on VLSI Circuits and the
International Solid-State Circuits Conference, in which he is the Chair of the
Analog Subcommittee. He has also served as a Guest Editor and Associate
Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS and the International
Journal of High Speed Electronics.
circuits in CMOS technology becomes increasingly more difficult
as device modeling faces new challenges in deep submicrometer
processes and emerging circuit applications. The sophisticated set
of characteristics used to represent today’s “digital” technologies
often proves inadequate for analog and RF design, mandating
many additional measurements and iterations to arrive at an
acceptable solution. This paper describes a set of characterization
vehicles that can be employed to quantify the analog behavior
of active and passive devices in CMOS processes, in particular,
properties that are not modeled accurately by SPICE parameters.
Test structures and circuits are introduced for measuring speed,
noise, linearity, loss, matching, and dc characteristics.
Index Terms—Analog circuits, device noise, mismatch, MOS
devices, RF circuits, technology characterization.
I. INTRODUCTION
AS CMOS technology continues to benefit from both
scaling and the enormous momentum of the digital
market, many high-speed and radio-frequency (RF) integrated
circuits that were once considered the exclusive domain of
III–V or silicon bipolar technologies are likely to appear as
CMOS implementations. However, issues such as technology
development costs, computer-aided design (CAD) infrastructure,
and fabrication turnaround time make it desirable to use
a single mainstream digital CMOS process for all IC products.
“Analog processes” may be approaching extinction.
The design of analog and RF circuits in a digital CMOS
technology faces many difficulties: the set of available active
and passive devices is quite limited, the technology is optimized
for digital design, and the devices are characterized and
modeled according to simple benchmarks such as current drive
and gate delay. While the first two issues can be somewhat
alleviated by circuit and architecture innovations, the quandary
of poor characterization leads to substantial conservatism in
analog design, thus resulting in circuits that do not exploit
the “raw” speed of the technology. In some cases, even
conservatism does not solve the problem, mandating lengthy
iterations in the design. For example, in a narrow-band RF
oscillator, it is difficult to guarantee a correct output frequency
without accurate data on device parasitics and their variation
with process and temperature.
This paper describes a set of technology characterization
methods that provide the basic information required in ana-
Manuscript received August 11, 1998; revised October 26, 1998.
The author is with the Electrical Engineering Department, University of
California, Los Angeles, CA 90095 USA.
Publisher Item Identifier S 0018-9200(99)01651-0.
Fig. 1. Analog design octagon.
log and RF design. It also reviews some relevant modeling
difficulties. Section II presents the motivation for and the
issues related to the task. Sections III and IV deal with
characterization for analog and RF design, respectively. For
the sake of brevity, we use the term “analog” to mean “analog
and RF.”
II. MOTIVATION AND ISSUES
The principal difficulty in using a digital CMOS technology
for analog design is that the process is optimized and
characterized for primarily one tradeoff: that between speed
and power dissipation. By contrast, analog circuits entail a
multidimensional design space. This is illustrated in Fig. 1,
where almost every two parameters trade with each other. The
true severity of these tradeoffs is known only if relevant data
have been obtained for the technology.
The need for specialized “analog characterization” arises
from two types of shortcomings: inaccurate modeling (e.g., the
output resistance of transistors or its nonlinearity) or simply
lack of modeling (e.g., self-resonance frequency of inductors
or matching properties of transistors). While efforts toward
improving submicrometer device models continue vigorously,
scaling appears to degrade the modeling accuracy faster. That
is, it seems that for no generation of CMOS devices have
models been sufficiently accurate.1
It is also important to note the rapid migration of digital
circuits from one generation of the technology to the next.
Analog circuits have historically lagged behind by more than
one generation, failing to utilize the full potential of new
processes or to comply with their supply-voltage scaling. A
solid understanding of the properties and limitations of devices
1 This is the author’s opinion rather than a documented fact.
0018–9200/99$10.00 ã 1999 IEEE
RAZAVI: CMOS TECHNOLOGY CHARACTERIZATION 269
also minimizes the number of design iterations and hence the
time to market.
The above observations indicate that analog design in a new
technology can be greatly simplified if measured data points
describing the analog behavior of devices and subcircuits are
obtained. In fact, such data points do become available as
analog designers begin to use a process, but in an ad hoc
manner and very slowly. A unified effort to collect all of the
necessary data soon after the qualification of a technology is
rarely seen.
Technology characterization for analog design nonetheless
involves a number of difficult issues.
• Owing to the lack of universally applicable analog benchmarks,
many test structures must be built to satisfy the
needs of various systems. Op-amps, filters, comparators,
data converters, oscillators, phase-locked loops, frequency
synthesizers, and RF transceivers incorporate many different
functions that heavily depend on poorly modeled
properties of devices.
• Some device characteristics, for example, capacitor mismatch
and thermal and noise, are difficult to measure.
Thus, proper circuits must be included on the die to allow
reliable measurement.
• Some measured properties are difficult to incorporate in
simulations. For example, the voltage dependence of the
output impedance of transistors cannot be easily included
in the simulation of an op-amp. Such cases may mandate
designing a complete circuit to measure the overall effect.
• The large number of test structures requires substantial
characterization time and effort. It is therefore desirable
to automate the measurements to the extent possible.
• The test structures and circuits must be designed such that
they can be ported into the next generation of the process
with minimal modifications.
It is also beneficial to design two sets of structures: a
comprehensive version to be used in the early phases of a
new technology and a brief version to be included in product
mask sets. The latter proves useful in detecting anomalies in
the process.
III. CHARACTERIZATION FOR ANALOG DESIGN
The device and circuit properties of interest in analog design
can be grouped into six categories:
1) dc behavior;
2) ac behavior;
3) linearity;
4) matching;
5) temperature dependence;
6) noise.
We consider the first five here and noise in Section IV. Our
emphasis is on those aspects that are not modeled accurately
in SPICE simulations.
Fig. 2. AC coupling using devices biased in subthreshold region.
A. DC Behavior
Typical – characterization seeks to minimize the
overall error in the curve fitting procedure, thus incurring
significant relative local errors. While advanced models such
as BSIM3v3 incorporate many parameters to lower such errors,
some submicrometer device properties still defy accurate representation.
For this reason, it is important to have measured
I–V data points in a range suitable to analog design, e.g.,
mV and A/ m.
Subthreshold characteristics of MOSFET’s are difficult to
model. (One version of the BSIM model does represent this
behavior, but it also yields a negative gate-source capacitance
under certain conditions.) In sampled-data circuits, the subthreshold
conduction of switches in the off state, especially
at high temperatures, may lead to significant leakage, thereby
corrupting the stored information. This effect also becomes
important in determining the lower bound on the speed of
dynamic latches in mixed-signal and digital circuits.
A difficulty in subthreshold modeling is dc and ac slope
discontinuity in the vicinity of strong inversion as increases.
In fact, time-domain simulation of circuits in which
MOSFET’s reciprocate between the two regions exhibit substantial
dynamic errors. For example, in two-tone simulations
of RF CMOS circuits, the output spectrum often suffers from
a high noise floor that is an artifact of slope discontinuities in
the device equations. This issue remains unresolved in most
mainstream models.
Subthreshold operation actually proves useful in some cases.
For example, as depicted in Fig. 2, a diode-connected MOSFET
biased in subthreshold exhibits a large incremental resistance,
thus creating a low cutoff frequency in the high-pass
filter formed with By contrast, a resistor of comparable
value would consume a large area and introduce considerable
parasitic capacitance at the output node. The circuit of Fig. 2
can be employed if the subthreshold properties of transistors
are known at different temperatures.
Another troublesome effect is the output resistance of shortchannel
MOS transistors, and in particular its variation with
the drain-source voltage even in the saturation region. Shown
in Fig. 3, this phenomenon causes the intrinsic gain to
depend on the output potential, thereby creating nonlinearity
in amplifiers. Present models include this behavior but with
more than 50% error in some cases. For op-amp design, it is
270 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999
Fig. 3. Measured variation of MOS output resistance versus VDS:
Fig. 4. Capacitance–voltage characteristic of an MOS device along with its
derivative.
also useful to obtain measured plots of as a function of
the drain current for various device dimensions.
B. AC Behavior
The discrepancy between the simulated and measured speed
of MOS devices and circuits continues to haunt designers. For
example, the device models extracted from a wafer often fail to
accurately predict the gate delay of ring oscillators fabricated
on the same wafer.
To obtain a versatile set of data points, ac characterization
of a technology must be performed at both device level and
circuit level. For devices, and must be measured under
bias conditions common in analog circuits, e.g.,
mV and A/ m. For a given
current, [1], indicating that the ’s
encountered in analog applications are much lower than those
measured with the value typically reported for
CMOS technologies.
Another ac device parameter of interest is the nonlinearity of
MOS gate-channel capacitance in accumulation and inversion.
This effect can be better seen by plotting the derivative of
the – data versus the gate-channel voltage (Fig. 4). While
MOS capacitors are quite nonlinear, they nonetheless prove
useful in some analog circuits [2].
MOS capacitors are also utilized as supply and bias bypass
elements (Fig. 5). In such cases, the series resistance of
the capacitor affects the effectiveness of the bypassing. For
example, the resistance can be used to produce a critically
damped response if lead inductance or current slew rates are
Fig. 5. MOS capacitors as bypass elements along with illustration of channel
resistance.
Fig. 6. N-well capacitance in a PMOS differential pair.
Fig. 7. Bias circuit using n-well resistor.
significant [3]. The series resistance is readily calculated in
the strong inversion region [4], but its value in accumulation
must be measured.
Another rarely available process parameter is the capacitance
of the n-well to the substrate. If the source and n-well of
a PMOS device are connected to avoid body effect (Fig. 6), the
n-well capacitance must be taken into account. The capacitance
of resistors made of n-well may also be important. In Fig. 7,
for example, resistor and capacitor isolate the bias
current mirror from the signal path, thus allowing ac coupling
of the input signal. In this circuit, the value of is not critical
so long as it remains much greater than the output impedance
of the preceding stage, but the parasitic capacitance of
attenuates the signal.
For ac characterization at circuit level, frequently used
building blocks such as ring oscillators can serve as test
vehicles. The choice of a circuit for this purpose is determined
by three factors: 1) the complexity and design time of the
circuit, 2) the useful information obtained from testing the
circuit, and 3) the level of difficulty in testing the circuit.
Differential ring oscillators with realistic device dimensions
and bias currents are more widely accepted than single-ended
RAZAVI: CMOS TECHNOLOGY CHARACTERIZATION 271
Fig. 8. Simple comparator for measuring metastability.
topologies. The speed of these circuits and its correlation with
process corner models constitute a more reliable basis for
design than those of ring oscillators using simple inverters.
Another circuit that exercises the intrinsic speed of the
technology is a voltage comparator. Fig. 8 shows an example
where and amplify the input difference and and
perform regeneration after turns off. The regeneration
speed at nodes and can be measured by operating
the comparator near metastability [5], [6] and measuring the
change in the response time for small increments in the input
voltage. In practice, all of the device widths and bias currents
may be scaled up by a factor of 100 so that the currents
provided by and generate moderate voltage swings
in a 50- instrumentation environment. Note that such scaling
does not change the regeneration time constant.
C. Linearity
The linearity of both passive and active devices plays a
critical role in many analog circuits. The value of a resistor
or a capacitor can be expressed in terms of the voltage across
the device as The coefficients
and must be measured for different types of resistors and
capacitors available in a process. Note that the linearity of
polysilicon resistors typically improves with their length [7].
The linearity of op-amps is also of great interest. In a
conservative design, the open-loop gain of the circuit is
chosen large enough to obtain a small closed-loop gain error,
thus guaranteeing that the nonlinearity is of the same order.
However, the low of submicrometer devices makes it
difficult to achieve a high open-loop gain. Furthermore, gain
error per se is not critical in many applications, or it can be
corrected by calibration techniques. Thus, aggressive designs
seek to minimize the nonlinearity by adequate open-loop gain.
This is possible only if the nonlinearity of the open-loop circuit
is well understood.
In a fully differential op-amp, e.g., Fig. 9(a), the nonlinearity
arises from two principal sources: compressive voltage-tocurrent
conversion of the input differential pair and the voltage
dependence of the output impedance of the cascode devices.
As depicted in Fig. 9(b), the first mechanism is measured by
applying a differential input voltage and monitoring the output
short-circuit current. Since the output voltage is constant, the
nonlinearity due to the cascode devices is negligible. For
the second mechanism, as shown in Fig. 9(c), the differential
input is set to zero and the output large-signal impedance is
measured.
To quantify the overall nonlinearity, we utilize the configuration
depicted in Fig. 10, where all the passive devices may
be external for simplicity. Resistors and establish the
bias but are large enough to be considered ac open. With a pure
sinusoid applied to the input and different choices of
the output harmonic contents can be measured and the “static”
nonlinearity of the open-loop op-amp derived.
D. Matching
While matching properties of passive and active devices
have been extensively studied in terms of dimensions and
process constants [8]–[11], actual measurement of mismatches
is often necessary. This is because in addition to fundamental
parameters such as device area, other characteristics such
as “cleanness” of the process determine the magnitude of
mismatches as well.
Measurement of transistor and resistor matching is straightforward.
The test structures must employ many different
dimensions so as to quantify the dependence on the area.
Fig. 11(a) shows an arrangement with a minimum number of
pads for measuring the gate-source voltage of each transistor
in every differential pair. A tail current is drawn from the
common source node of the pair, node or node is tied to
, and the other is connected to ground, thus establishing
the value of Using this technique, the mismatch
can be measured as a function of the drain current. The
resistor–capacitor network prevents oscillations due to large
parasitic inductances in the setup.
It is also desirable to include nominally identical current
sources [Fig. 11(b)]. Since the mismatch between two current
sources depends on both the threshold voltage mismatch
and mismatch [11], [6], measurements on both
structures in Fig. 11(a) and (b) allow for cross checking the
validity of the extracted data.
Measurement of resistor mismatch usually requires a fourpoint
(“force” and “sense”) arrangement so as to avoid resis-
272 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999
Fig. 9. (a) Sources of nonlinearity in a folded-cascode op-amp, (b) measurement of input nonlinearity, and (c) measurement of output nonlinearity.
(Common-mode feedback not shown.)
Fig. 10. Arrangement for measuring op-amp distortion.
tance mismatches due to external connections. The topology
shown in Fig. 12 allows such a measurement with a relatively
small number of pads.
Characterization of capacitor matching is quite difficult.
For small capacitors used in most analog circuits, in the
range of 0.1–1 pF, direct measurement would suffer from
many uncertainties resulting from parasitics in the physical
setup. Thus, the capacitors must be isolated from external
connections by means of on-chip circuitry. Fig. 13 illustrates
an efficient approach to measuring capacitor mismatch [12].
The top plates of and are connected to node , and
a PMOS source follower serves as a buffer. The n-well of
is tied to its source to eliminate the nonlinearity due
Fig. 11. Structures for measuring transistor mismatch.
to body effect. The test proceeds by applying a ramp to
while is grounded, generating a ramp at whose slope
is approximately equal to Next, and
are interchanged, and the output slope
is obtained. The relative mismatch can then be calculated as
(1)
Utilizing only the change in this approach cancels
the effect of three nonidealities: 1) the initial charge at node
, 2) the parasitic capacitance at node , including the input
RAZAVI: CMOS TECHNOLOGY CHARACTERIZATION 273
Fig. 12. Topology for measuring resistor mismatch.
Fig. 13. Capacitor mismatch measurement.
capacitance of the source follower, and 3) the drain-source
impedance of [12]. The measurement must nonetheless
be performed with relatively large voltage excursions so as to
calculate the difference between and accurately.
E. Temperature Dependence
The temperature variations of many device parameters are
not modeled accurately in SPICE. Examples include output
resistance, subthreshold conduction, and capacitances. Furthermore,
the temperature coefficient of resistors and capacitors
must be measured for each technology generation, as it may
depend on doping levels or the type of dielectrics.
In addition to basic device parameters, some other circuitrelated
quantities should also be characterized as a function
of temperature. For example, direct measurement of the variations
of the transconductance, on-resistance, and threshold
voltage provides a more reliable and versatile characterization,
thus simplifying the design procedure. The ac properties of the
technology also vary with temperature. The ring oscillator and
comparator circuits described in Section III-B can serve as
structures allowing the measurement of speed as a function of
temperature.
Owing to the lack of comprehensive data on temperature
dependence of device parameters, a number of important
design questions remain unanswered: How should the bias
currents of an op-amp vary with temperature? What is the
optimum temperature variation of bias currents in a low-noise
amplifier or mixer? How should the tail currents of a ring
oscillator or LC oscillator vary with temperature? To answer
these questions, various dc and ac temperature dependencies
of devices must be measured and incorporated in simulations.
Another useful test structure is a simple bandgap reference
[13]. Depicted in Fig. 14, such a circuit finds wide usage
in most analog and mixed-signal systems. With a simple
Fig. 14. Simple bandgap reference. (Transistor M5 serves as startup.)
version of the reference available in the early phases of
technology qualification, subsequent iterations in the design
are minimized. In addition, measurement of the base resistance
and current gain of individual vertical pnp transistors proves
useful in predicting the behavior of the bandgap circuit.
IV. CHARACTERIZATION FOR RF DESIGN
Most of the analog characterization methods described
above are also essential to RF design. For example, dc and
ac properties, noise, and temperature dependence are critical
here as well. In addition, many RF characteristics must be
measured at device and circuit levels to facilitate the design
of highly integrated RF systems.
A. Device Properties
The severe tradeoffs among noise, frequency of operation,
gain, and power dissipation in RF circuits limit the number
of active devices in the signal path of some building blocks.
Examples include low-noise amplifiers (LNA’s), mixers, and
oscillators. Consequently, passive monolithic devices that exhibit
little loss and operate as high-quality loads or interfaces
can greatly simplify the design. Inductors, capacitors, varactors,
and transformers appear in many RF IC’s today.
While the value of spiral inductors can be calculated with
reasonable accuracy [14], the and self-resonance frequency
are much more difficult to predict. The distributed nature of
the spiral and the underlying substrate usually requires the use
of finite element analysis, especially for complex structures
such as stacked inductors [15]. Furthermore, the dependence of
inductor parameters upon line width and spacing, the number
of turns, the size of the opening in the middle, and the type of
“shield” placed underneath the inductor [16] make it difficult
to choose the optimum structure for a given frequency of
operation. For these reasons, it is beneficial to obtain measured
data for parameters of inductors with different geometries.
Shown in Fig. 15 are two structures of interest in RF design
[21].
A simple method of measuring the and the self-resonance
frequency of inductors is illustrated in Fig. 16. Identical
inductors and together with the negative- pair
and form an oscillator. If the capacitance contributed
274 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999
(a) (b)
Fig. 15. (a) Inductor with broken shield and (b) stacked inductors.
Fig. 16. Arrangement for measuring self-resonance frequency and Q of
inductors.
Fig. 17. Floating varactor in CMOS technology.
by the transistors and the output buffer is negligible with
respect to the parasitic capacitance of and the circuit
oscillates at In this case, the buffer can incorporate small
devices so as to present minimal capacitance to the oscillator
(at the cost of signal attenuation) because most spectrum
analyzers can detect the existence and frequency of even weak
oscillations.We also observe that if the tail current is decreased
to the point where the oscillation is near failure, the negative
transconductance provided by and is approximately
equal to the equivalent parallel resistance of the inductors,
i.e., Thus, The
value of under this condition can be measured for and
which are identical to and The key point here
is that the and self-resonance frequency are measured in a
realistic environment.
Varactors built in CMOS technology also suffer from a
low quality factor. Depicted in Fig. 17, a floating varactor
exhibits substantial series resistance due to the n-well material.
Direct measurement of the varactor provides an equivalent
lumped value for the three-dimensional distributed resistance
of the structure. MOS varactors have also been studied recently
[22]–[24] and merit characterization in each process.
Another useful passive component is a transformer.
Monolithic transformers suffer from parasitic capacitances
and frequency-dependent voltage and power loss [25], [26].
Measurement of these parameters can lead to a model suited to
circuit simulations. For interfaces where voltage gain is more
important than power gain, the 2 : 1 transformer of Fig. 18(a)
may prove useful. A simple transformer-based oscillator, e.g.,
that in Fig. 18(b), can also yield the self-resonance frequency
and loss of the structure.
B. Noise
The thermal noise of submicrometer MOS transistors
does not satisfy the long-channel approximation
[17]. Depending on the bias conditions, the
“excess noise factor” may be quite higher than 2/3, an effect
not included in most SPICE models. More accurate models for
the channel noise are described in [18]. But two other thermal
noise mechanisms merit characterization as well. Illustrated
in Fig. 19, the first results from the capacitive coupling of
the drain noise current to the gate, introducing a physical
gate noise current [19], [20]. To measure this phenomenon,
different noiseless impedance levels can be placed in series
with the gate while other parameters remain constant, thereby
producing different noise levels in the drain current.
The second effect arises from the modulation of the threshold
voltage by the body thermal noise [Fig. 19(b)]. Note that,
owing to the distributed nature of the body resistance, this
issue exists in differential circuits as well. Fig. 20 plots the
simulated noise figure of a cascode stage as the body resistance
varies, revealing a degradation of approximately 0.2 dB. The
principal difficulty here is accurate prediction of the local body
resistance—the three-dimensional structure may require the
use of device simulators.
The noise of MOSFET’s has also created challenges in
analog and RF design. For noise calculations, the technology
constant in must be measured for
both PMOS and NMOS devices. In reality, the dependence on
and even may be of the form where and
are nonunity exponents. These parameters too may vary from
one process to another.
Direct measurement of device noise is quite difficult simply
because the values to be measured are too small to be sensed
properly by typical instrumentation. Some amplification is
therefore necessary, but the noise contributed by the gain
RAZAVI: CMOS TECHNOLOGY CHARACTERIZATION 275
(a) (b)
Fig. 18. (a) A 2 : 1 transformer and (b) a transformer-based oscillator.
(a) (b)
Fig. 19. Illustration of (a) drain noise capacitively coupled to gate and (b)
modulation of threshold voltage by body thermal noise.
Fig. 20. Noise figure of a cascode amplifier as a function of the body
resistance (modeled by a lumped resistor in series with the substrate terminal
of each device).
stage(s) must be sufficiently lower than that of the device
under test.
Fig. 21 shows an arrangement for measurement of both
thermal and noise of MOSFET’s. Biased by means of
and the transistor under test, forms a cascode
configuration with providing an intrinsic voltage gain
of approximately The external resistor is
chosen to be higher than the output impedance of the cascode
to avoid lowering the voltage gain. A high value for also
minimizes its noise contribution. Note that the effect of the
noise generated by is negligible at low frequencies if
exceeds approximately four.
The large value of together with typical bias currents
used in the test translates to a relatively high supply voltage,
but can be maintained below the maximum allowable value
to avoid stressing the cascode device. To minimize drifts in
some dc feedback may be added from to the gate of
The source follower lowers the output impedance
of the circuit, an important provision because the input noise
current of the external sensing circuitry may be significant.
Fig. 21. Arrangement for measuring device noise.
Since power supplies and bias networks typically exhibit
considerable noise, the circuit of Fig. 21 must be operated
from a low-noise battery. Furthermore, the supply line, the
gate-source bias of , and the gate bias of must be
bypassed to ground by several capacitors ranging from a few
nanofarads to several hundred microfarads so that unwanted
low-frequency and high-frequency noise components are suppressed.
C. Circuit Properties
The design of such RF building blocks as LNA’s, mixers,
oscillators, modulators, and power amplifiers (PA’s) heavily
depends on the overall transceiver architecture and the intended
wireless standard. For this reason, it is difficult to
introduce test vehicles that provide useful data for various RF
applications. For example, the design of an LNA that must
drive a 50- load may be significantly different from one
that need not. Thus, RF characterization circuits are somewhat
specialized.
A critical issue in today’s RF CMOS design is the substantial
variability of device and circuit parameters with process
and temperature. While analog circuits have for decades utilized
tracking and cancellation techniques to achieve welldefined,
stable parameters, RF circuits still lack such precautions.
For example, since the gain of LC-tuned amplifiers
is a strong function of parasitic capacitances, it must be
measured on various wafers from different lots so as to obtain a
realistic distribution. Similarly, the center frequency of typical
oscillators, e.g., that in Fig. 16, must be measured on many
dice and at temperature extremes to yield the required tuning
range.
276 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999
Fig. 22. Arrangement for measuring phase and gain mismatch between two
RF mixers.
Matching properties play an important role in many RF
circuits. Fig. 22 illustrates an example of measuring the
phase and gain mismatch between two RF mixers. The highfrequency
inputs and directly drive the two mixers to
avoid mismatches in the external connections. If the frequency
difference between the two inputs is relatively small,
and have a low frequency, and hence their phase and
amplitude mismatch can be measured with high precision.
Another useful benchmark is a frequency divider. Divideby-
two circuits and dual-modulus dividers find wide usage in
quadrature generation and frequency synthesis, respectively.
At present, the power–speed tradeoff of these circuits is
much more severe in CMOS technology than in bipolar
implementations. Furthermore, significant discrepancy is often
observed between the simulated and measured speed–power
tradeoff of the circuits. Thus, measured data corresponding to
different divider topologies prove valuable.
PA’s are also critical components whose design remains
a formidable task. Owing to the large current and voltage
changes that the output transistor in a PA experiences, accurate
device modeling to predict efficiency and linearity has become
a serious issue. As a result, PA design heavily relies on the
data measured for single transistors. Large MOSFET’s with
proper layout and pad configurations must be included to allow
high-power, high-frequency characterization.
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Behzad Razavi (S’87–M’90) received the B.Sc. degree
from Sharif University of Technology, Tehran,
Iran, in 1985 and the M.Sc. and Ph.D. degrees
from Stanford University, Stanford, CA, in 1988
and 1992, respectively, all in electrical engineering.
He was with AT&T Bell Laboratories, Holmdel,
NJ, and subsequently Hewlett-Packard Laboratories,
Palo Alto, CA. Since September 1996, he has been
an Associate Professor of electrical engineering
at the University of California, Los Angeles. His
current research includes wireless transceivers, frequency synthesizers, phaselocking
and clock recovery for high-speed data communications, and data
converters. He was an Adjunct Professor at Princeton University, Princeton,
NJ, from 1992 to 1994 and at Stanford University in 1995. He is the author of
Principles of Data Conversion System Design (New York: IEEE Press, 1995)
and RF Microelectronics (Englewood Cliffs, NJ: Prentice-Hall, 1998), and the
Editor of Monolithic Phase-Locked Loops and Clock Recovery Circuits (New
York: IEEE Press, 1996).
Prof. Razavi received the Beatrice Winner Award for Editorial Excellence
at the 1994 ISSCC, the Best Paper Award at the 1994 European Solid-State
Circuits Conference, the Best Panel Award at the 1995 and 1997 ISSCC,
and the TRW Innovative Teaching Award in 1997. He is a member of the
Technical Program Committees of the Symposium on VLSI Circuits and the
International Solid-State Circuits Conference, in which he is the Chair of the
Analog Subcommittee. He has also served as a Guest Editor and Associate
Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS and the International
Journal of High Speed Electronics.
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