VerifEye Probe Netlist Syntax — Ansoft Designer 7.0 在线帮助文档，Ansys Designer 教程

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VerifEye Probe Netlist Syntax

The Eye Probe contains the DFE setup. The netlist syntax for the VerifEye Probe is:

AEYEPROBExxxx n1 [n2] COMPONENT=EYE_PROBE
+ SOURCE_NAME='source_name'
+ DFE_TAPS=val
+ DFE_LOCS=[ locations ]
+ DFE_WEIGHTS=[ weights ]
+ DECISION_HIGH=val
+ DECISION_LOW=val
+ DECISION_THRESHOLD=val
+ CTLE_FIRST_POLE=val
+ CTLE_SECOND_POLE=val
+ CTLE_ALLOWED_GAIN=[val ...]

n1 is the node connected to the single-ended source. n2 is the second node on a differential probe. The entry COMPONENT=EYE_PROBE is required.

**Eye Probe Parameters**
Parameter	Description	Unit	Default
SOURCE_NAME	Name of the associated eye source enclosed in quotes	None	None
DFE_TAPS	Number of DFE taps	None	0
DFE_LOCS	Bit locations of DFE taps	None	None
DFE_WEIGHTS	DFE weights	None	None
DECISION_HIGH	Decision high value	Volt
DECISION_LOW	Decision low value	Volt	None
DECISION_THRESHOLD	Decision threshold	Volt	None
CTLE_FIRST_POLE	Frequency of first pole in Continuous-Time Linear Equalization (CTLE) transfer function. Setting CTLE_FIRST_POLE enables CTLE.	Hz	None
CTLE_SECOND_POLE	Frequency of second, parasitic pole in CTLE transfer function (optional). Ignored if CTLE_FIRST_POLE is not set.	Hz	None
CTLE_ALLOWED_GAIN	Bracketed list of one or more allowable gain values separated by spaces. If CTLE_ALLOWED_GAIN is not present, Nexxim calculates the optimum gain between -infinity dB and 0 dB (linear values 0 to 1). Ignored if CTLE_FIRST_POLE is not set.	dB	Calculated


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