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Nexxim Simulator >
Nexsys Discrete Time Domain Analysis >
   Nexsys Simulation of a Mixed Mode Topology >
       Nexsys Partitioning and Scheduling Process           


Nexsys Partitioning and Scheduling Process

Prior to running the discrete time system simulation, Nexsys partitions the mixed mode system, converting the mixed-mode topology to a purely functional topology where the signal flow is unidirectional. Electrical subcircuits must be modeled functionally or behaviorally after accounting for all impedance mismatches, noise, and other electrical effects.

After finishing the partitioning is completed, the process of scheduling all components inside the system for discrete time simulation begins. Since discrete time signals flow unidirectionally from input to output, the order in which components are scheduled is critical during discrete time simulation.

The scheduling process begins with the source components in the system and then iteratively schedules each remaining component (after ensuring that all components leading to the input of that component have already been scheduled). A SAMPLER component is placed at the physical/functional interface where each Nexxim source connects to a Nexsys component. The sampling rate specified for the SAMPLER sets the Nexsys timestep.

During partitioning, Nexsys packs each set of connected electrical components into an internal functional model based on the signal type (baseband or bandpass) of the input to the electrical components.

Nexsys Transient Cosimulation Model

When the input signal type is baseband, Nexsys uses a Transient Cosimulation model (tran_cosim_model). When the Nexsys time domain simulation encounters a tran_cosim_model, the transient analysis engine is invoked and stays open during the course of the simulation. Data is exchanged at each time step between the top-level Nexsys simulator and the transient engine. (see Figure 3)

Envelope Cosimulation Model

When the input signal type is bandpass, Nexsys uses an Envelope Cosimulation model (envelope_cosim_model).

An ENVELOPEADAPTOR component must be placed at the interface of a bandpass or modulated signal entering a Nexxim subcircuit from a Nexsys functional component. The ENVELOPEADAPTOR component helps the simulation engine to partition the system for simulation and to select the appropriate analysis for the Nexxim subcircuit.

The envelope_cosim_model employs two simulation strategies, one for linear subcircuits and another for nonlinear subcircuits such as amplifiers, mixers, and frequency multipliers.

Linear Subcircuits. When the sub-circuit is linear, the top level Nexsys simulation engine calls Nexxim Linear Network analysis (LNA) to obtain the frequency response and convert it to the time domain impulse response. Convolution is then used to calculate the output signal. (see Figure 4).

Nonlinear Subcircuits. When the Envelope Cosimulation model sub-circuit is nonlinear, the top level Nexsys simulation engine runs Nexxim Envelope Analysis to solve the circuit and interactively exchange data as described above for the tran_cosim_model. (See Figure 5) .

Scheduling Feedback Loops

Scheduling of feedback loops starts with the first component in the feed-forward path and continues around the loop until the feedback input is reached. To prevent a possible deadlock in the discrete time simulation of a feedback loop, the feedback signal in the loop is primed at time t=0 with one discrete time sample having a zero value. The user instead can force the priming to occur anywhere inside the feedback loop by placing an RDELAY or CDELAY component at the desired priming point. If the simulator does not detect the presence of any RDELAY or CDELAY components in the feedback loop, Nexsys automatically performs the minimum number of primings needed to resolve the deadlock.

An example of a simple feedback loop is the phase locked loop example shown in Figure 6.

To break the deadlock, the feedback signal leading to the input of the complex subtractor CSUB (the component with the minus sign) is initially primed with a zero sample.




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