Assumptions During System Partitioning for Discrete Time Signal Analysis — Ansoft Designer 7.0 在线帮助文档，Ansys Designer 教程

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Assumptions During System Partitioning for Discrete Time Signal Analysis

1. The impedance seen by an electrical component or sub-design looking into an input port of a functional component is assumed to be Rin, always defaulted to an open or infinity Ω (see Figure 2). In other words, when an electrical component or sub-design port is terminated into the input port of a functional component, the termination resistance is Rin. This load resistance can be adjusted by assigning a different value to the Rin parameter of the functional component. This resistance will have no noise contribution.

2. The impedance seen by an electrical component or sub-design looking into an output port of a functional component is assumed to be Rout (defaulted to a short or 0Ω) as shown in Figure 2. In other words, when an electrical component or sub-design input port is connected to the output port of a functional component, the assumed source resistance is Rout. This source resistance can be adjusted by assigning a different value to the Rout parameter of the functional component. Note that in reference to Figure 2, the input voltage to the electrical sub-design V2 would equal f(V1) if the impedance seen by the functional component looking into the electrical sub-design is 50Ω, provided that Rout is set to 50Ω. The notation f(.) represents the equivalent signal processing operation of the functional component.

3. The impedance seen by a functional component looking into an input port of another functional component is assumed to be Rin (typically defaulted to infinity) and the impedance seen by a functional component looking into an output port of another functional component is assumed to be Rout (typically defaulted to zero). This is illustrated in Figure 3 below.

4. All nonlinear electrical two-port components are assumed to be unidirectional (i.e., S₁₂ = 0). Each nonlinear electrical component is partitioned into three segments: a linear active input stage, a nonlinear functional stage followed by an output linear electrical passive stage. This arrangement will be discussed later in more details.

5. During signal analysis, any signal path in the system is described by its complex envelope and carrier frequency (i.e., the triplet (I(t), Q(t), f_c)) as well as the simulation time step t_s. It is extremely important to realize that, in general, the signal ((I(t), Q(t)) information bandwidth, carrier frequency f_c, and simulation time step t_s do vary from one point in the system to another. The user must be fully aware of the signal ((I(t), Q(t)) information bandwidth, the carrier frequency f_c, and simulation time step t_s at each point in the system to generate meaningful results.


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