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Ansoft Designer / Ansys Designer 在线帮助文档：

System Simulator >
System Component Models >
Vector >
   Merge Two Buses (BUSMERGE)       

Merge Two Buses (BUSMERGE)

 

 


Property

Description

Units

Default

Range/Type

RIN1

Input1 impedance

Ohm

Inf

(0, Inf]/Real

RIN2

Input2 impedance

Ohm

Inf

(0, Inf]/Real

ROUT

Output impedance

Ohm

0

[0, Inf)/Real

Ports

Input1

First input signal (complex vector)

Input2

Second imput signal (complex vector)

Output

Output signal (complex vector)

 

Notes

This model merges two buses (or vectors). Suppose the first bus input has a width W1 and the sec­ond bus input has a width W2, then the output bus has a width W1 + W2. The first W1 entries of the output bus comes from the first bus, the next W2 entries comes from the second bus.

Netlist Form

BUSMERGE:NAME n1 n2 n3 [Rin1=val] [Rin2=val] [Rout=val]

 

Netlist Example

BUSMERGE:1 1 2 3



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