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Current-Controlled Voltage Source, Multi-Input Gate

Current-Controlled Voltage Source, Multi-Input Gate

CCVS Gate Netlist Format

The format for an N-input AND gate CCVS is:

Hxxxx out+ out- [CCVS] AND(N) vin1 ... vinN

minval1 outval1 ... minvalK outvalK

[DELTA=val] [TC1=val] [TC2=val]

[SCALE=val] [M=val] [ABS=0|1]

The format for an N-input NAND gate CCVS is:

Hxxxx out+ out- [CCVS] NAND(N) vin1 ... vinN

minval1 outval1 ... minvalK outvalK

[DELTA=val] [TC1=val] [TC2=val]

[SCALE=val] [M=val] [ABS=0|1]

The format for an N-input OR gate CCVS is:

Hxxxx out+ out- [CCVS] OR(N) vin1 ... vinN

minval1 outval1 ... minvalK outvalK

[DELTA=val] [TC1=val] [TC2=val]

[SCALE=val] [M=val] [ABS=0|1]

The format for an N-input NOR gate CCVS is:

Hxxxx out+ out- [CCVS] NOR(N) vin1 ... vinN

minval1 outval1 ... minvalK outvalK

[DELTA=val] [TC1=val] [TC2=val]

[SCALE=val] [M=val] [ABS=0|1]

out+ and out- are the nodes of the voltage output. The entry CCVS is the default for the H element type. vin1 ... vinN are the voltage sources through which the multiple control current inputs flow. The number of input sources (N) in the list must be the same as the value specified for AND(N), NAND(N), OR(N), or NOR(N). For current-controlled sources, N must be in the range 2£N£4.

**Multi-Input Gate CCVS Instance Parameters**
Parameter	Description	Unit	Default
ABS	Output is absolute when ABS=1	None	0
DELTA	Distance over which curvature is applied in the interpolation function Zero produces linear interpolation, positive values produce continuous curvature over the waveform Maximum is one-half of the smallest difference between control (input) values	None	One-fourth of the smallest difference between control (input) values
M	Multiplier to simulate multiple elements	None	1.0
SCALE	Scale factor for voltage	None	1.0
TC1	Linear (1st-order) temperature coefficient	°K^-1	0.0
TC2	Quadratic (2nd-order) temperature coefficient	°K^-2	0.0

CCVS Gate Netlist Examples

These two-input examples assume logic “0” is 0.0 volts output at 0.0 mA input, and logic “1” is 5.0 volts output at 5.0 mA input.

Hand2 30 0 CCVS AND(2) V21 V22
+ 0.0 0.0
+ 0.5e-3 0.1
+ 1.0e-3 0.2
+ 4.0e-3 4.5
+ 4.5e-3 4.75
+ 5.0e-3 5.0

Hnand2 40 0 CCVS NAND(2) V23 V24
+ 0.0 5.0
+ 0.5e-3 4.75
+ 1.0e-3 4.5
+ 4.0e-3 0.2
+ 4.5e-3 0.1
+ 5.0e-3 0.0

Hor2 50 0 CCVS OR(2) V25 V26
+ 0.0 0.0
+ 0.5e-3 0.1
+ 1.0e-3 0.2
+ 4.0e-3 4.5
+ 4.5e-3 4.75
+ 5.0e-3 5.0

Hnor2 60 0 CCVS NOR(2) V27 V28
+ 0.0 5.0
+ 0.5e-3 4.75
+ 1.0e-3 4.5
+ 4.0e-3 0.2
+ 4.5e-3 0.1
+ 5.0e-3 0.0

See the examples for the VCVS Multi-Input Gate element for samples of simulation runs produced by these devices.

Notes

The output is specified as a function of the inputs using a set of pairs (minval, outval or maxval, outval), separated by spaces and/or commas. Currents are specified in amperes, voltages in volts. The pairs should be entered in ascending order of minval or maxval (see Netlist Examples). Any number of pairs may be specified.

Notes

For AND and NAND gates, the simulator finds the minimum current across all voltage source inputs:

minI = MIN[I(vin1), I(vin2), ... I(vinN)]

The simulator matches minI to the list of entries minval1 ... minvalK in the instance statement, and sets the output to the corresponding outval.

When minI is equal to the current that represents logic “0” or logic “1,” the corresponding output from an AND or NAND gate should be set accordingly.

Values of minI that are intermediate between the logic “0” and “1” currents represent transitional values. For intermediate values that are not in the list of minvals, the simulator calculates the corresponding output by interpolation from the given values. The use of the DELTA parameter allows you to control the curvature of the interpolation to guarantee that the 1st derivative of the curve is continuous.

For values of minI that are below the range of listed input current, the simulator sets the output voltage to the one corresponding to the smallest input voltage in the list. For values of minI that are above the range of listed input currents, the simulator sets the output voltage to the one corresponding to the largest input current in the list.

For OR and NOR gates, the simulator finds the maximum difference between all pairs of inputs:

maxI = MAX[I(vin1), I(vin2), ... I(vinN)]

The simulator matches maxI to the list of entries maxval1 ... maxvalK in the instance statement, and sets the output to the corresponding outval.

When maxI is equal to the current that represents logic “0” or logic “1,” the corresponding output from an OR or NOR gate should be set accordingly.

Values of maxI that are intermediate between the logic “0” and “1” current represent transitional values. For intermediate values that are not in the list, the simulator calculates the corresponding output by linear interpolation from the given values, using the DELTA parameter as discussed above. See Netlist Examples below.

For values of maxI that are below the range of listed input currents, the simulator sets the output voltage to the one corresponding to the smallest input voltage in the list. For values of maxI that are above the range of listed input currents, the simulator sets the output voltage to the one corresponding to the largest input current in the list.

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